Re: busses

[Steven Rubin]

> I am trying to find a happy medium for things such as layout viewing,
> small simulations and schematic creation. I have tinkered with
> Electric for a couple of years and really like it a great deal. I have
> spent several hours over the last day trying to figure out the use of
> busses. I can correctly create them and 'rip' signals from them for my
> scats. However I cannot seem to figure out how to use them in
> simulations. Say for the sake of simplicity I want to create a
> schematic of eight invertors all of which receive their input from one
> of the eight wide bus's signals. I draw the invertors...good. Now
> what? The bus must start somewhere although it can terminate in
> space. How do I do this? So far I have tried drawing a buffer and
> starting the bus from there but what is the input to the buffer? I
> tried making it a bus as well but whan I try to simulate the beast I
> get complaints that I am using more signals than the buffer has
> ports. Pardon me if this doesn't make sense. I have minimal experience
> with bus use and sometimes the questions are hard to form. Perhaps
> someone could provide me a simple example that is simulatable so I can
> model after that?

What you want to do is this:

(1) Make an schematic inverter.
(2) Create an icon for that inverter
(3) Place that icon into another facet and (this is new in 6.05) give it an 
arrayed name (set its node name to somthing like "m[0:7]").
(4) Now connect 8-wide busses to the icon and simulate.  You don't have to 
rip the busses, just give them names that are 8-long.  Note that another 
new feature in 6.05 is multidimensional busses, so you could call this bus 
(or even the arrayed instance) "xx[0:1][3:0]", or even "frank[a,b][c,d][0:1]".

Note that, because this is a new concept in Electric, arrayed nodes are not 
understood by all simulation netlisters.  It will work only in SPICE, 
Verilog, and IRSIM.

    -Steven Rubin