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Re: Segmentation Violation at sillicon compiler placement
From: |
Naohiko Shimizu |
Subject: |
Re: Segmentation Violation at sillicon compiler placement |
Date: |
Tue, 4 Nov 2003 08:04:45 +0900 |
Thank you Dr. Rubin,
It works fine with the option setting.
I will use Electric for my class in stead of Magic in the
next semester.
For EDIF generation with Icarus Verilog, I am in the half way.
Then I will try as soon as possible.
I also want to import Alliance's scalable standard cell library
to Electric for the EDIF. I am now working on MOSIS compatible
design rule definition for Alliance.
Perhaps I will need more study on Electric and help for these works.
Regards,
Naohiko Shimizu
http://shimizu-lab.dt.u-tokai.ac.jp/