RE: [Discuss-gnuradio] Using USRP as a DTV channel simulator

[Torell Kent-P12255]

Generating good white noise in real time with this bandwidth is a problem; it 
takes a lot of processing, particularly to get a good distribution with 
gaussian tails many sigma out.  If you're going to redesign the guts of the 
FPGA, I'd suggest feeding an external white noise generator into one of the a/d 
ports.  Then you'd set the summation level and bandwidth by register settings 
in the FPGA.  You could also use this port to sum external environment into the 
signal, such as narrowband tones, etc.

Dynamic multipath would be a little more complicated.  You could certainly do 
fixed multipath using an fir filter in the FPGA and work at the A/D sample 
rate, although I'm not sure how many resources are left on the fpga.

This could be very useful product for the USRP platform, essentially a channel 
simulator, where you'd feed a signal into an A/D port, massage the signal with 
distortion being generated by gnu software, and output the distorted signal 
through a D/A port.  This would also work with any of the transceiver boards 
being developed.

Kent Torell 

-----Original Message-----
From: address@hidden
[mailto:address@hidden Behalf
Of Damien B.
Sent: Thursday, March 31, 2005 9:15 PM
To: address@hidden
Subject: [Discuss-gnuradio] Using USRP as a DTV channel simulator


Hi everyone,

Our project is to use the USRP as a DTV channel simulator to test the
respective quality of DTV set boxes. That means to be able to
attenuate the signal, add noise and simulate echos from reflexions on
mountains for example.

The biggest question is how to do it. One way would be to record a
signal on the PC, then filter it and fire it back to the set box. But
we don't know if the speed of the hdd is fast enough for the mass of
data.

And other way would be to tune the FPGA firmware to implement all the
function inside. That is to receive the signal, create a really long
FIR with only a few non null coefficients and add a noise before
sending it back. Ideally the FIR should be configurable but we can
imagine to use a set of precompiled firmware to suit the testing
procedure.

Which approach is more sensible? I'm efficient in VHDL and verilog
doesn't seams to hard to learn. Does the existing FIR could be tune
for this application? Would the community be interested in this
alternative use of an USRP?

Regards
Damien


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