Re: [Discuss-gnuradio] Block diagram of FPGA interface

[Matt Ettus]

Quoting "Damien B." <address@hidden>:

> Hi Matt,
> I came up with the same diagram with a few difference. Could you confirm them
> ?
>
> - the cordic stage in TX chain is disable (V0.8)
>
> - DA converter can work at 128MS/s but the txsync is muxing at 32MS/s
> for each channel

Sort of.  The AD9862 CODEC chip has its own CORDIC on the TX side, so the TX
CORDIC is not in the FPGA.  Also, we send TX samples out of the FPGA at 32
MS/s.  The 9862 uses its CORDIC rotator on those for fine frequency adjustment,
then runs 2 halfband filters to convert up to 128 MS/s, and then does coarse
frequency adjustment on that.

Effectively, you can think of it as:

    interpolate to 128 MS/s then do digital upconversion (DUC) using a cordic to
get to the desired frequency.

Matt