Re: [Discuss-gnuradio] tx mux explained!

[Eric Blossom]

On Thu, Aug 25, 2005 at 03:40:13PM -0400, cswiger wrote:
> I guess the most direct question is: with a tx mux of 0x0008
> why am I getting any signal out of J49?   Only DAC0 should
> be enabled, and connected to the I output of DUC0.
> 
> --Chuck

Good question.  The answer is a bit involved.  Let me try and explain.

First, take a look at figure 3 on page 19 of the AD9862 data sheet.
It shows the components of the transmit path in the AD9862.

We've got these blocks enabled:

  Block D: the "Fine Modulator"  -- this is a digital up-converter
  Block C: interpolation filter (we interpolate by 4 in the AD9862)
  Block B: the "Coarse Modulator" 
  Block A: the actual DACs.

Block E, the Hilbert filter, is disabled.


In the FPGA transmit path, we perform part of the interpolation (all
but the final factor of 4) and the routing of the outputs of the
FPGA interpolators to the appropriate pins on the 9862's.  (Taking
advantage of the DUCs in the AD9862s saves us tons of FPGA resources.)

The DAC mux in the FPGA controls which output of which FPGA
interpolator is connected to which of the 4 logical TxDATA busses.
(fine point: the AD9862 muxes two channels of DAC input over a single
set of pins).

Looking at page 20 of the data sheet, "Transmit Applications Section",
we've got the 9862 configured for "Dual Channel Complex DAC Data (I &
Q or Single Sideband)".  This means that the DACs are logically
paired, since we're using Block D, the on-chip digital up-converter.

So, from the point of view of the software, when bit 0x8 in the tx mux
register is not set, you are sending zero's to the corresponding
TXDATA bus.  Remember that the AD9862 digital up-converter is downstream
from there.

Here's the verilog (usrp_std.v):

   // dac{0,1,2,3}mux are the 4 bit mux registers for each FPGA "DAC" path.
   // {i,q}_out_{0,1} is the output of the FPGA interpolators.
   // tx_{a,b}_{a,b} are the signals that connect to the 4 TXDATA buses of the 
2 9862s.

   wire [15:0] tx_a_a = dac0mux[3] ? (dac0mux[1] ? (dac0mux[0] ? q_out_1 : 
i_out_1) : (dac0mux[0] ? q_out_0 : i_out_0)) : 16'b0;
   wire [15:0] tx_b_a = dac1mux[3] ? (dac1mux[1] ? (dac1mux[0] ? q_out_1 : 
i_out_1) : (dac1mux[0] ? q_out_0 : i_out_0)) : 16'b0;
   wire [15:0] tx_a_b = dac2mux[3] ? (dac2mux[1] ? (dac2mux[0] ? q_out_1 : 
i_out_1) : (dac2mux[0] ? q_out_0 : i_out_0)) : 16'b0;
   wire [15:0] tx_b_b = dac3mux[3] ? (dac3mux[1] ? (dac3mux[0] ? q_out_1 : 
i_out_1) : (dac3mux[0] ? q_out_0 : i_out_0)) : 16'b0;


So, returning to the AD9862, if either of a pair of DACs is enabled,
you're going to see output from both of them.  Also, there's no way short of
cycling power to reset the phase accumulators in the AD9862 NCOs.  So
if the DUC tx frequency has ever been set to non-zero, and then
returned to zero, you have a probability near 1 of having a non-zero
phase in the 9862 NCO which will cause the output of the I/Q pair to
be rotated.

Hope this helps!

Eric