Hello! I am trying to implement a CSMA/CA typish MAC layer protocol. something like RTS-CTS-DATA-ACK type packet exchange. The idea to move some functionality on FPGA. The idea is to maintain two speperate buffers, one for DATA packets and the other for RTS packets. so that over multiple rounds of transmissions, DATA packet is preprocessed and stored on FPGA..yeilding in good deal of time saving.
Also implementing some timers on FPGA which would assist in collision avoidance mechanism.
I just wanted a sanity check from you guys who have worked on design and use of FPGA.
on a course level i could see, from std_usrp project,
57% of the memory bits are utilised so far: there is scope for extra buffer 87% of LEs are also utilised. :
So would there be enough space to implement the control logic? (will need to implement inside the master_control module right?).
if there is not enough space, can I kick out few modules? Also how control signaling is done?...it must be inline to data path I guess? whats the protocol for it?