[Discuss-gnuradio] FPGA bit file -- again

[Angilberto Muniz Sb]

I guess my message got into a black hole :-)

Anyone has an idea where I can find the files
"cic_inter_2stage.v" and "cic_decim_2stage.v" ??

As we can see, they are referenced on the "ddc.v"
file:

cic_decim_2stage #(.bw(bw),.N(4)) 
                decim_i(.clock(clock),.reset(reset),.enable(enable),
                
.strobe1(1'b1),.strobe2(strobe2),.strobe3(strobe1),.shift1(shift2),.shift2(shift1),
                        .signal_in(i_cordic_out),.signal_out(i_out));


Or if they doesnt exist at all, it means the "ddc.v"
code is never compiled? If so, how come we have 1,2 or
4 DDC in the system?

Thankx,

Angilberto.


==============================
From:  Angilberto Muniz Sb 
Subject:  [Discuss-gnuradio] FPGA bit file -- again 
Date:  Mon, 12 Dec 2005 16:46:05 -0800 (PST) 

--------------------------------------------------------------------------------

I'm trying to bypass the hardware DDC/DUC and tying to
implement the FPGA based UP/DOWN conveters.

Looking into 'ddc.v' and 'duc.v' we see references to
'cic_decim_2stage' and 'cic_interp_2stage'
respectively, but there are no '.v' equivalent files
-- the close to it are 'cic_interp.v' and
'cic_decim.v' -- 

I assume the '_2state' refers to '2nd stage decimating
and interpolating' -- Am I right?

Is it just tipo error? If so, how come I get no error
compiling the project under Quartus?

Thank you,

Angilberto.



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