I'm trying to use my logic analyzer to measure the received noise. Here is how I proceed to do that. First in the verilog code, I connect the 12 bit rx_a_a ADC input to the io_rx_a DEBUG output by adding this line of code:
assign io_rx_a = {4'b0000, rx_a_a }
I also make sure that the outputs of the io_pins.v module are not connected to anything. (especially the io_rx_a output) That way, only rx_a_a should be connected to the io_rx_a output.
I then load the .rbf file to the FPGA, connect the io_rx_a outputs of the LFRX daughter board to the logic analyzer and observe what I get. I make sure that no antenna is connected to the RX-A port. To my surprise, some of the upper bits toggle. For example, bit 11, 10, 9, 8, 5 ,4 , 3 ,2 ,1 0, toggle. Since I should only be getting noise, I was expecting to get a very low signal where only the least significant bit would be switiching between low and high values.
Does anyone know what could be the origin of such results? Any insight would be greatly appreciated.