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Re: [Discuss-gnuradio] DBSRX, I2C Interface Verification


From: Matt Ettus
Subject: Re: [Discuss-gnuradio] DBSRX, I2C Interface Verification
Date: Thu, 08 Feb 2007 18:37:05 -0800
User-agent: Thunderbird 1.5.0.9 (X11/20070104)

Gregory W Heckler wrote:
> I'm in the process of debugging my DBSRX driver, and have verified the
> following:
>
> 1) The GC1 input voltage from the aux_dac can be properly commanded.
> Verification was carried out by probing the GC1 pin on the Max2118
> chip, and observing the voltage sweep from .75 to 2.6 Volts.
>
> 2) The enable_refclk and set_refclk_divisor work. This was verified by
> probing the Xtal+ pin on the Max2118 chip, and observing the expected
> clock frequency based on the commanded divisor (4 MHz for a divisor
> value of 16).
>
> 3) Read of Max2118 status. After a power cycle reading 2 bytes from
> the I2C interface reports back values of 64, and 127. Reading again
> results in values of 0 and 127 (the PWR status bit has been cleared).
>
> Unfortunately nothing else is working. The charge pump calibration
> procedure keeps failing due to the 3 ADC PLL bits being zero every
> time I read the Max2118 status. I need to verify that the I2C write
> commands are getting through to the Max2118. For the Max2118 3 bytes
> are written over the I2C to write a single register, they are:
>
> 1) (Device address<<1) + write bit
> 2) Register address (0...5)
> 3) Register value
>
> I noticed that in the python code the first byte is left out, is this
> taken care of by the FPGA? Has anyone tried to turn on the diagnostic
> features of the Max2118 to get a clock signal out of the CNTOUT pin?
> I've tried setting the DIAG value to 6 in order to output the result
> of the R divider onto the CNTOUT pin, but when I probe the pin there
> is no signal. Thanks for any clues.

One other thing to keep in mind is that the PLL takes time to lock, so
you may need to wait before trying the next VCO.

Matt




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