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Re: [Discuss-gnuradio] Re: transmitting two independent Signals


From: Eric Blossom
Subject: Re: [Discuss-gnuradio] Re: transmitting two independent Signals
Date: Wed, 21 Feb 2007 07:20:42 -0800
User-agent: Mutt/1.5.9i

On Wed, Feb 21, 2007 at 11:11:17AM +0100, anmar wrote:
> Eric Blossom wrote:
> > On Tue, Feb 20, 2007 at 03:41:31PM +0100, anmar wrote:
> >> hi all,
> >> 
> >> we have been searching for a way to transmit two independent signals one
> >> on TxA and the other on TxB.
> > 
> > Using two daughterboards, you can send different complex baseband
> > signals out the A side d'board and the B side d'board.  You must set
> > nchan=2 in the usrp.sink_c constructor, and provide an interleaved
> > stream of complexes.  (Yes, the interface is a bit strange and ought
> > to be revisited/fixed.)  You can create the interleaved output stream
> > using
> > 
> >   u = usrp.sink_c(nchan=2, interp_rate=<interp>)
> > 
> >   src0 = <first complex source>
> >   src1 = <second complex source>
> >   interleaver = gr.interleave(gr.sizeof_gr_complex)
> >   fg.connect(src0, (interleaver, 0))
> >   fg.connect(src1, (interleaver, 1))
> >   fg.connect(interleaver, u)
> > 
> >   r0 = u.tune(0, u.db[0][0], freq_0)   # set center freq on side A 
> > d'board
> >   r1 = u.tune(1, u.db[1][0], freq_1)   # set center freq on side B 
> > d'board
> > 
> 
> Hi Eric,
> thanks for your answer,
> 
> > That's right.  If you're using a single Basic Tx daughterboard, and
> > you want independent real output out the I and Q, that'll take a fair
> > amount of hacking.  Using two daughterboards is going to be much, much
> > easier ;)
> 
> ok that is to bad, but do you know any one how tried to do this

No.

> or do you know where to begin hacking :)?

Getting this right requires understanding how the host, the FPGA code
and the AD9862 all interact.  If you've been following Brian's
questions about the FPGA over the past few days, you're on the right
track.  Note also, that if you send two real signals to the AD9862 you
lose the use of the digital up converter ("Fine Modulator") in the
AD9862.  Assuming you need a DUC, you'll have to reimplement this
functionality in the FPGA.  [In "two independent real signal mode" you
only have Block C "Interpolator" and Block B "Coarse Modulator"
available.]

> We just want to see if it can be done with the time that we have, or 
> just go and use two Tx daugterboards.

Any particular reason you don't want to use two Tx daughterboards?  
If you use two Tx daughterboards, you could have your independent-signal
transmitter up and working in 30 minutes.

Eric


[FYI, your mail tool seems to be hard-coding the Reply-To address to
point to list.  This is somewhat inconvenient in that it keeps readers
from being able to select between replying to the list or replying to
only you.]




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