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[Discuss-gnuradio] start/end of burst issues


From: Zhuocheng Yang
Subject: [Discuss-gnuradio] start/end of burst issues
Date: Fri, 3 Aug 2007 16:34:19 -0400 (EDT)
User-agent: SquirrelMail/1.5.1 [CVS]

Hi guys:

Here is the problem. If I receive a packet whose timestamp is out of date, I 
trash the packet. If there are packets afterwards that is a continuation of the 
first packet, I should trash those as well despite the fact that their 
timestamp indicates now. (They belong to the same high level packet, if the 
first one can not be sent, why bother sending the later ones). The way to tell 
if a packet is a continuation of the earlier ones is by burst flags. The start 
of burst flag indicate the start of a sequence of packets and the end of burst 
flag indicate the end of that sequence.

Under svn directory 
http://gnuradio.org/svn/branches/developers/zhuochen/inband/usrp/fpga/inband_lib
there are two files, chan_fifo_reader.v and channel_ram.v that are responsible 
for storing incoming usb_data into ram and sending it accordingly. 
channel_ram.v accepts incoming packets, store them in its ram and outputs 
packets with rd signal. Chan_fifo_reader on the other hand sends the packets 
and discard any packets with expired timestamp.

Under svn directory
http://gnuradio.org/svn/branches/developers/zhuochen/simulation/burst_test
there are three files, test_chan_fifo_reader.v, strobe_gen.v and math_real.v
that can be used as testbenches to the two files above. 

In the test_chan_fifo_reader.v I send a seqence of packets with expired 
timestamp and then a seqence of packets with future timestamp. When I run the 
simulation, the sequences of packets with expired timestamp got discarded and 
the sequences of packets with the future timestamp is delayed and then sent. So 
everything looks fine.

However, when I upload the whole thing to the board and my partner send me a 
sequence of packets with expired timestamp, only the packet with start of burst 
got discarded. The later packets did not get discarded even though they are 
continuations of the first one. 

I don't understand why there is a difference in behavior between the simulation 
and the board, can anyone take a look at my files and give me some pointers?

Leo 






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