[Discuss-gnuradio] Running a Test Simulation of FPGA Code with Quartus

[Reid N Kleckner]

Hello,

I've written a small Verilog module for the FPGA on the USRP to do phase
recovery.  I'd like to test it in isolation before I try it out on the board,
but I'm having major problems feeding Quartus two 16 bit sine and cosine
signals with a random phase offset.  The idea is that q_out after the phase
locked loop should be zero for this case, and noise for a real signal.  It
seems that the only tools for generating signals within Quartus basically let
you manually specify integer levels for bit vectors and a bunch of other things
for single bit wires.  The alternative to using their powerless signal
generation system is to import some waveform files, the formats of which can be
vwf/cvwf, vec, tbl, scf, and vcd.  Vcd and vwf/cvwf are Quartus specific and the
others are mostly compatibility layers with Max+Plus and such.  Does anyone know
of a tool that can generate sine waves and export waveforms in these formats? 
Or do people just burn their Verilog code to the board to test it?

Thanks,
Reid