Re: [Discuss-gnuradio] Capturing 12-bit data at 10MHz sample clock?

[Martin Dvh]

Dan Halperin wrote:
>> From poking around, it appears to me that the data transfer across the
>> USB is either 2 * 8 bits/sample or 2 * 16. 2 * 12 should be easy enough
>> to disentangle?
> It'll involve hacking the FPGA code, but no, it shouldn't be especially
> hard.
The problem with 12 bit code is that it does not fit 1:1 in 16 bit streams.
This means that you must send halve samples to the PC. and the driver must know 
which is MSB and which is LSB determined by the position in the
512 byte USB packet.

But it can be done of course.

One other way is using the new m-block code.
This supports much more flexibility on what data formats you send over the bus.


> 
> -Dan
> 
> Jan Schiefer wrote:
>> This may be a dumb question, but suppose I changed the USRP ADC clock to
>> 10MHz.
If you just change the 64 MHZ clock, this means that the FPGA will also run on 
10 MHz.
I am not sure that the communication with the FX2 chip (USB chip) will still 
work because the FX2 runs at 48 MHz.





> Would there be a way to get 12-bit integer data across the USB,
>> using usrp_rx_cfile.py or something similar? This would result in a
>> manageable USB transfer rate of 30MB/s and line up pretty well with the
>> bandwidth of the TVRX tuner.
The bandwith of the TVRX is 6 MHz. and it uses real sampling (not complex)
That means you need a sampling freq of at least 12 MHz.
This could be converted inside the FPGA to a 6 Msamples/sec complex stream.

Since the IF of the TVRX is located at 44 MHz, you also need to consider where 
the niquist freq lies.


The TVRX uses real sampling of an IF of 44 MHz (or was it 48 MHz).
This goes well with a 64 Msamples/sec samplerate.
The niquist frequency is 64/2 = 32 Mhz, so you get the 44 Mhz mirrored about 
this which results in a IF freq seen by the FPGA at 20 MHz (which
is about 6 MHz wide).
This is downconverted by the cordic in the FPGA to a complex IF at 0. which can 
the be decimated to the rate you want.


This whole story will not work with a 10 Msamples/sec samplerate.
the 44 MHz will mirror around to 4 MHz and be 6 MHz wide.
This means from 1 to 7 Mhz.
But the niquist freq of 10 Msamples/sec is 5 Mhz, which lies inside the 1 - 7 
Mhz range.


A better way is running the ADC and FPGA at 40 MHz.
The IF will come out at 4 Mhz  (1 to 7 MHz) but this time your samplerate is 
high enough.
You can then decimate by 4 inside the FPGA, like it is done now.

Yet another way involves no clock change at all.
I have been working with fractional rate decimaters/interpolators inside the 
USRP FPGA.
You can put a fractional rate decimater inside the FPGA which decimates by 6.4.

It is a bit hard to get them to fit but you get a lot of flexibility out of 
them without changing the clocks.


> 


> 
>> Just curious,
>>    Jan
> 
> 
>> _______________________________________________
>> Discuss-gnuradio mailing list
>> address@hidden
>> http://lists.gnu.org/mailman/listinfo/discuss-gnuradio
> 

_______________________________________________
Discuss-gnuradio mailing list
address@hidden
http://lists.gnu.org/mailman/listinfo/discuss-gnuradio