Re: [Discuss-gnuradio] ADC questions

[Brian Padalino]

On Tue, Sep 23, 2008 at 4:08 PM, Sebastiaan Heunis <address@hidden> wrote:
> Brian
>
> Thanks for the reply.  I see from this Verilog line that the adc input
> gets sign extended and gets 3 zeros at the back as you mentioned.
>
> rx_dcoffset #(`FR_ADC_OFFSET_0)
> rx_dcoffset0(.clock(clock),.enable(dco_en[0]),.reset(reset),.adc_in({adc0[11],adc0,3'b0}),.adc_out(adc0_corr),
>                                                
> .serial_addr(serial_addr),.serial_data(serial_data),.serial_strobe(serial_strobe));
>
> I just don't know how the rx_dcoffset part works.  I don't know where
> in the c++ or Python code the FR_ADC_OFFSET registers get written, so
> I can't follow it that well.  Does this remove a DC offset introduced
> by the ADC chip?

The ADC doesn't introduce any DC offset - the signal on the analog
pins just may have some DC offset.  The rx_dcoffset comepnsation
module just does a long running average of the signal and subtracts
out the DC component before shipping the signal off.

> What I'm busy doing is to test the Verilog code with iverilog.  I want
> to know how input samples should look that I am using to test the
> different FPGA blocks.  If I, for instance, generate an FM signal that
> I want to send into the cordic block, do I generate a signal and
> convert it to 12-bit two's complement, extend the sign bit and pad it
> with 3 zeros at the beginning to get it to 16-bits?  Can I then send
> this signal to the cordic block and assume that this is what it would
> look like in the FPGA?

Is your FM signal at a carrier or at baseband?  If it's at baseband,
you need to send it in two different ports - one for the I and one for
the Q, and bypass the CORDIC.  If it is at some residual carrier and
requires mixing down, then you need to just set it to one input port
and set the CORDIC phase accumulator to be equal to the negative of
the residual carrier to mix the signal back down to baseband.

> What does the AGC level sensing part in adc_interface do?  Does this
> monitor the level of the incoming samples to see if clipping occurs?
> The last part, the mux, only routes the different adc inputs to the
> correct DDC channels in the FPGA, right?

As for the AGC and mux, I believe you are correct - but I am no
authority on the subject.

Good luck with your simulation.

Brian