I'm at svn revision 10441 - with both the firmware and fpga code built
from that (using Xilinx ISE 10.1 to make the fpga). I've just modified
the txrx.c code - adding:
clocks_enable_test_clk(true, 2);
clocks_mimo_config(MC_WE_LOCK_TO_SMA);
just before the while(1) loop
My rx_mimo.cc code also calls ->config_mimo(MC_WE_LOCK_TO_SMA), but
right now I've stepped back to just getting one USRP2 synchronized to my
external source - which in this case is a function generator with a
10MHz sine with 2V P-P.
Is it possible some of the hardware on my USRP2's isn't working?