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Re: [Discuss-gnuradio] reading two rx channels on usrp2
From: |
Tom Gross |
Subject: |
Re: [Discuss-gnuradio] reading two rx channels on usrp2 |
Date: |
Wed, 27 Jan 2010 13:54:39 -0500 |
thanks Johnathan and Eric, I'm glad I asked before spending too much
time trying to make this work! :-)
Johnathan, the custom FPGA firmware you describe sounds like it might
be perfect for what we want to do, provided it's not impossible to
demux the data stream. I haven't seen any usrp2 FPGA sources (they
don't appear to be in either the 3.2.2 or 3.3.3 tarballs) - I guess
this means I need to figure out the new "git" stuff...
it sounds like I will need to get a Xilinx compiler to build them,
once I find them.
On Wed, Jan 27, 2010 at 1:23 PM, Johnathan Corgan
<address@hidden> wrote:
> On Wed, Jan 27, 2010 at 10:05, Eric Blossom <address@hidden> wrote:
>
>> See comment above about there currently being only a single DDC in the
>> FPGA. If you want two channels, amongst other things, you'll need to
>> instantiate two DDCs, and add code that interleaves the samples from
>> the two DDCs. You'll also have to create host and firmware that can
>> select the 1 or 2 channel case.
>
> There is a custom USRP2 top-level FPGA build that creates two
> synchronous DDCs (they share a CORDIC NCO phase accumulator) in the
> usrp2/fpga/top/u2_rev3_2rx_iad directory. It is designed to
> synchronously sample the two inputs of a BasicRX or LFRX as separate
> real signals.
>
> (It also implements an integrate-and-dump decimator instead of the CIC
> and HB, for unrelated reasons.)
>
> The complex outputs of the two DDCs are interleaved and placed into a
> single data stream, are started and stopped at the same time, and
> share a common frequency and decimation rate. Thus, the host and
> firmware code are unchanged. If this serves your purpose, it would be
> a good place to start. It does sound like, though, from your original
> post, that you are looking to have independent streams, and the above
> won't help you.
>
> Johnathan
>