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Re: [Discuss-gnuradio] Building USRP2 FPGA on ISE 11.4


From: Jared Casper
Subject: Re: [Discuss-gnuradio] Building USRP2 FPGA on ISE 11.4
Date: Wed, 17 Feb 2010 10:00:10 -0800

On Mon, Feb 15, 2010 at 6:59 PM, Tracey Bernath <address@hidden> wrote:
> Nope, Nope, and Nope. I was rather shocked, things never go that well for me
> :)
>
> I pulled the u2_rev3 and just resolved my way through the source tree. I was
> not expecting it to generate cleanly. I did regenerate two cores as part of
> the process, dumped a couple of the generated .v files because they refused
> to resolve properly, but the first time through they regenerated and went
> right through place and route with no errors, and no timing issues like I
> had with it earlier (set to the -4 speed grade).
>
> I just havent been able to generate the bitstream, and I won't have a chance
> to do any testing til next week, if I do get it resolved.
>

Just for another data point, on 64 bit linux running ISE 11.4, I
pulled directly from git, did "touch <...>/coregen/*", and make proj,
make synth, then make bin in u2_rev3, and got a bit file okay.  Bitgen
gave an info message about the Match_cycle change, but otherwise just
normal warnings about dangling ram pins and built the bit file just
fine (although I haven't actually tested it on the usrp2 yet).
There were some warnings about deprecated options in the project early
on, but they seemed more or less harmless.

I'm not sure how your coregen cores got regenerated.  ISE 11.4 has
fifo generator 5.3, while the .xco files in coregen/* are for version
4.3 (which is why I had to touch all those files so it wouldn't try to
rebuild them, but just use the existing .ngcs)

Jared




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