Has there ever been any discussion of adding an I/Q imbalance correction block into the Rx chain in the FPGA image on the USRP/USRP2? On past systems that I've worked on, the calibration procedure to get this imbalance reduced can take quite a long time and still only produces moderately improved results. An alternate approach, of course, is simply to fix it digitally. One example write-up of this can be found here:
I know that Bob McGwier has also been doing a bunch of work recently to tackle this problem, and would be interested if any additional details of this work are available yet.
Anyway, we've tested the aforementioned paper's scheme, and it works quite well. Its really just a couple of complex multiplies, once you have the correction parameters determined (which will be frequency and/or hardware dependent).
If there is any interest here, we'd be happy to submit a patch to the FPGA codebase to add this capability in. And for people who don't need it, the block can simply be bypassed.