[Discuss-gnuradio] Modified verilog code for smaller FPGA

[Andy Blueman]

Hi all!

I'm new to GNU Radio and USRP. I'm making a prototype of 
data transmission system based on USRP, but
in future I want to use 
much smaller FPGA. I will not deal with GNU Radio or python at all, I 
need to create a 
verilog code that could fit into much smaller FPGA. 
My requirements 
are 2 megabit/second on transmission and same on receiving of data. I 
only need 1 complex 
channel on transmission and one on receiving 
side. I read manual and see that it can be easily done using config 
file, 
but i need the actual Verilog code with only one channel each way, so I 
want to get rid of some comb-filters in DUC and DDC.
I wonder if 
someone has done anything like this before? Some guidelines would be 
highly appreciated!

Thanks!