On Thu, Sep 1, 2011 at 8:42 AM, Wolfarth, Ryan
<address@hidden> wrote:
Hi all,
I am generating my masters thesis proposal and I have a few questions about the capabilities of the E100 and the feasibility of my project. I have read other posts to gather information, but correct me if anything I've determined is wrong. My goal is to implement an 8 channel GPS L2C receiver on an FPGA. I am interested in doing this with the E100 since I may be able to take advantage of the ARM processor as well. Can anyone with experience in this area provide advice?
I would like to use the RFX1200 to receive the L2C signal since it has better performance characteristics than the DBSRX. This would prevent me from first acquiring L1 signals to aid in acquisition, so I propose using preloaded almanac data to estimate SV position/Doppler frequency. This would reduce the number computations when acquiring L2 CM code. The end result only has to go as far as to decode the navigation bits: I will not need a position solution.
The root of my question is: does the FPGA on the E100 have enough space to handle this project?
Does it sound like I'm on the right track?
Sounds like a very interesting project. I have two suggestions:
1. The SBX daughterboard has a better noise figure (5dB vs. 8dB typ.), with better linearity, and would be better suited for GPS work, especially if you aren't using front-end filters. SBX will also receive both the L1 and L2 frequencies.
2. The E110 is identical to the E100 except that it uses the XC3SD3400A FPGA instead of XC3SD1800A, and so has additional FPGA resources.
Best,
--n
Thank you in advance!
Ryan Wolfarth
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