Many thanks to the members of this community that my responded to my previous query. They were most helpful. I will have you know that the status of my endeavor of sending SMS messages over CDMA has accumulated momentum and my determination escalates with every passing milestone. I have never been one to quit on a challenge.
I'm wondering if someone out there can further explain this rather perplexing segment in the top level verilog code. It appears that I and Q signals have been swapped, and that one rail has had the bits inverted. The comment "inverted to facilitate clean layout" causes me sleepless nights and minor bouts of indigestion. Why is this bit inversion performed? As I have modified the transmit path and send my own 2's complement data, shall I keep this inversion in the code or is it to conform only to something done in the default FPGA build? Also, why is the negative edge of the clock used?
wire [15:0] dac_a_int, dac_b_int; // DAC A and B are swapped in schematic to facilitate clean layout // DAC A is also inverted in schematic to facilitate clean layout always @(negedge dsp_clk) DACA <= ~dac_b_int;
always @(negedge dsp_clk) DACB <= dac_a_int;
Much appreciation to any helpful tidbits which the group can contribute to remedying this quandary.