Re: [Discuss-gnuradio] Phase measurement with Ettus Research N210

[Daniele Nicolodi]

I don't speak Verilog but I get the general gist of the code below.

Thanks. Cheers,
Daniele


On 18/06/2014 01:09, Stephen Harrison wrote:
> The Verilog source for the USRP N210 is available online. You can see
> this in ddc_chain.v:
> 
>   wire [31:0] phase_inc;
>    reg [31:0]  phase;
> ...
> 
>    setting_reg #(.my_addr(BASE+0)) sr_0
>      (.clk(clk),.rst(rst),.strobe(set_stb),.addr(set_addr),
>       .in(set_data),.out(phase_inc),.changed());
> ...
> 
>    // NCO
>    always @(posedge clk)
>      if(rst)
>        phase <= 0;
>      else if(~ddc_enb)
>        phase <= 0;
>      else
>        phase <= phase + phase_inc;
> ...
> 
>    // CORDIC  24-bit I/O
>    cordic_z24 #(.bitwidth(cwidth))
>      cordic(.clock(clk), .reset(rst), .enable(ddc_enb),
>    .xi(to_cordic_i),. yi(to_cordic_q), .zi(phase[31:32-zwidth]),
>    .xo(i_cordic),.yo(q_cordic),.zo() );
> 
> 
> 
> 
> On Tue, Jun 17, 2014 at 4:02 PM, Daniele Nicolodi <address@hidden
> <mailto:address@hidden>> wrote:
> 
>     Thanks for the answers.
> 
>     I didn't think that the sine wave in the FPGA were generated with an
>     integer phase accumulator (I don't know much about how signal processing
>     is done in FPGAs).  If this is the case, as I understand from Stephen
>     email, now I know where the frequency error comes from.
> 
>     On the other hand, I think that the fact that the sine is computed via
>     the CORDIC method may introduce numerical errors in the amplitude only,
>     which would not result in a frequency systematic error.
> 
>     Cheers,
>     Daniele
> 
>     On 18/06/2014 00:43, Stephen Harrison wrote:
>     > Just some quick calculations in python:
>     >
>     > exact phase increment for 10 MHz:
>     >
>     >>>> (10e6/100e6)*2**32
>     > 429496729.6
>     >
>     > Closest phase increment:
>     >
>     >>>> np.round((10e6/100e6)*2**32)
>     > 429496730.0
>     >
>     > Resulting frequency:
>     >
>     >>>> (np.round(10e6/100e6*2**32)/2**32)*100e6
>     > 10000000.009313226
>     >
>     > We are out by 9.3mHz!
>     >
>     >
>     > On Tue, Jun 17, 2014 at 3:36 PM, Sylvain Munaut <address@hidden
>     <mailto:address@hidden>
>     > <mailto:address@hidden <mailto:address@hidden>>> wrote:
>     >
>     >     Hi,
>     >
>     >     > To start I want to characterize the phase noise of the device,
>     >     therefore
>     >     > I send to both the RX channel and to the frequency reference
>     input the
>     >     > same 10 MHz signal. I configured the N210 for 200 kHz
>     sampling and a
>     >     > carrier frequency of 10 MHz.
>     >
>     >     The LFTRX doesn't have a tuner so if you set a carrier freq of
>     10 MHz
>     >     the frequency shift is done by the FPGA via CORDIC and  you'll
>     have
>     >     numerical errors in there. You just can't get rid of them.
>     >
>     >
>     >     Cheers,
>     >
>     >        Sylvain
>     >
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> 
>