Hello all,
I am testing a QPSK Tx/Rx I made in grc across two USRP N210's. I can demodulate and decode the data fine at the receiver to produce the bits I transmitted. The problem is, when watching the frequency sink at the output of the USRP source (picture attached), there is typically 4 seconds of latency between making a change at the transmitter and seeing the change at the frequency sink block. I'm worried this is a bad sign of things to come.
My sample rate is already near the lower limit of what the USRP N210 requires (200k). At his rate, I don't see any D's being produced in the terminal over short run times. I haven't left the flowgraph running for a long time. When I increase the sample rate to 400k, I begin seeing D's in the terminal. I noticed that when I run the python script for the receiver, whichever core it is currently running on pegs at 100% usage.
My question is, looking at my receiver flowgraph, would you think this design should push the limits of a good laptop? Would you believe I could be constrained to near the lowest sample rate limit with this design?
qpsk_rx_v0.grc.png