Re: [Discuss-gnuradio] Interleaved sampling without interleaved clocks?

[madengr]

In the spirit of voiding the warranty, physically invert the LVDS clock input
and output traces at the ADS62P48 with haywire and x-acto knife; the FPGA
may then not know the difference.  Use it as sub-device A:AB at the full 200
Msps, then interleave the complex parts into a real stream once in GR. 
Anyway, thanks for the info.

Lou


Matt Ettus wrote
> Lou,
> 
> Many high-speed data converters actually interleave samples from multiple
> lower speed ADCs.  They delay clock, rather than the signal, which is much
> easier.  Even then, unless the delay is perfect, you get really bad spurs.
> Mismatches in delay on the order of 100 fs can be a big problem.
> 
> So what you want to try should be possible, but the results aren't going
> to
> be stellar.  The ADCs are set up for simultaneous sampling at 200 MHz or
> 5ns.  You would need to split the signal and then delay one leg by 2.5ns.
> No hilbert transforms or phasing networks are required.
> 
> You *might* also be able to get the clock generator chip to generate an
> inverted clock to the 2nd ADC chip, in which case you wouldn't need the
> delay.
> 
> In both cases, you're going to need to do some FPGA work to get the
> samples
> lined up in the right order.
> 
> Matt
> 
> 
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