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Hi Ihab
For frequency higher than 6 Ghz, a down converter can be
used to over come this problem.
Exactly what we're saying!
I think it can handle this rate. Please correct me if i'm
Wrong.
You might be wrong! As said, this is a hard task, and it's very hard
to make things scale up on many CPUs, especially if there's
dependence between data or steps - as is the case for anything
decision aided, things like iterative decoders, long convolutional
codes, etc.
If you successfully implement something that does this high-rate
decoding on your CPUs alone, it'd definitely grab quite some
attention from the SDR community.
- There are (synchronizers,
equalizers, channel codes etc) blocks in the gr-dvbt
project why I cant use them?
You can! But they are special-purpose for DVB-T. They might or might
not be appropriate for your application and your channel.
- when you mentioned channel coding do you mean that i need to
create a new one? and Why would I need it?
Because Channel coding is what you do to get a good BER with limited
SNR, and it is typically a trade-off between computational
complexity, error recovery/detection performance and suitability for
the type of symbol error combinations you're expecting.
- If i need BCH performance Why is difficult to achieve?
Sorry, I don't understand
- if the data requirement is fine (CPU and etc), what is the
best way to start building the receiver? How can I figure out
the blocks That i need for this receiver?
Start small! Have you been through the GNU Radio tutorials on
http://tutorials.gnuradio.org? If you feel comfortable after
reading these, dive into adapting existing things (gr-dvbt is really
a good choice), and find out where your transceiver BER bottlenecks
and where your computational bottlenecks come from.
Best regards,
Marcus
On 24.08.2016 16:12, Ihab Zine wrote:
Hi Ron and Marcus,
For frequency higher than 6 Ghz, a down converter can be
used to over come this problem.
for the data rate and bandwidth, the PC i'm using has the
following specifications:
Architecture: x86_64
CPU op-mode(s): 32-bit, 64-bit
Byte Order: Little Endian
CPU(s): 20
On-line CPU(s) list: 0-19
Thread(s) per core: 2
Core(s) per socket: 10
Socket(s): 1
NUMA node(s): 1
Vendor ID: GenuineIntel
CPU family: 6
Model: 63
Model name: Intel(R) Xeon(R) CPU E5-2660 v3 @
2.60GHz
Stepping: 2
CPU MHz: 1553.804
CPU max MHz: 3300.0000
CPU min MHz: 1200.0000
BogoMIPS: 5197.32
Virtualization: VT-x
L1d cache: 32K
L1i cache: 32K
L2 cache: 256K
L3 cache: 25600K
NUMA node0 CPU(s): 0-19
I think it can handle this rate. Please correct me if i'm
Wrong.
i have other questions:
- There are (synchronizers,
equalizers, channel codes etc) blocks in the
gr-dvbt project why I cant use them?
- when you mentioned channel coding do you mean that i
need to create a new one? and Why would I need it?
- If i need BCH performance Why is difficult to achieve?
- if the data requirement is fine (CPU and etc), what is
the best way to start building the receiver? How can I
figure out the blocks That i need for this receiver?
Regards
Ihab
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