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From: | Bowen Hu |
Subject: | Re: [Discuss-gnuradio] GSoC19: The proposal draft of Verilog Design Simulation Integration |
Date: | Fri, 22 Mar 2019 08:41:14 +0000 |
Hi
Carlos,
Thank you for your advice. It will definitely be great if not only Verilog simulation, but also VHDL simulation was integrated into the GNU radio. I will try to keep the code as independent
as possible, and reserve the interface in order to support VHDL later.
Regards,
Bowen
From: Carlos Alberto Ruiz Naranjo <address@hidden>
Sent: Thursday, March 21, 2019 17:15 To: Bowen Hu Cc: address@hidden Subject: Re: [Discuss-gnuradio] GSoC19: The proposal draft of Verilog Design Simulation Integration The idea of simulating VHDL modules with GNURadio is great.
It might be interesting to create something generic that can interact with a VHDL simulator (like GHDL) or with cocotb.
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