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Re: Nonlinear distortion of USRP


From: Marcus D. Leech
Subject: Re: Nonlinear distortion of USRP
Date: Mon, 6 Jun 2022 09:19:19 -0400
User-agent: Mozilla/5.0 (X11; Linux x86_64; rv:91.0) Gecko/20100101 Thunderbird/91.9.1

On 2022-06-05 23:33, 能书能言 wrote:
Hi,
    Recently, I am confused about the process from baseband signal to RF transmission. I know that baseband signal is sent to USRP through UHD. If the signal amplitude exceeds 1, what will happen? I looked up some mailing lists and mentioned nonlinearity. I wonder what this nonlinearity means? There are many nonlinear devices in RF, such as ADC, amplifier, etc. which is the specific one?     As I understood it earlier, suppose a baseband signal sample (0.8+0.8i) becomes Udacmax* (0.8+0.8i) when it enters the USRP. Udacmax is the maximum voltage. When a signal sample is (2+2i), it becomes udacmax* (1+1i)?Amplitudes exceeding 1 are forced to be limited to 1 and multiplied by the maximum voltage?     When the baseband signal has a high PAPR, it will affect the RF operation. A high amplitude will bring nonlinear distortion to the power amplifier. Is this nonlinear distortion the same as the nonlinearity brought by the amplitude exceeding 1 mentioned above? If  it is the same, can I evaluate the impact of high PAPR by changing the value of the "multiply const" module (the scaling factor before the baseband signal enters the USRP sink) to make the signal enter nonlinearity?      Finally, I would like to know the whole process from baseband signal to RF electromagnetic wave (on USRP). Is there any website you can recommend? I have some fragmentary knowledge of signal processing, but I can't combine them to figure out the whole process.
     Looking forward to your reply, thanks in advance!
Sincerely,
Regards
                     linge93

There is a convention established in the SDR world that floating-point baseband signals are *scaled* into {-1.0,+1.0}.  The hardware then scales this internally into the ranges that   are appropriate for the DAC and ADCs involved, after possibly performing DUC (Digital Upconversion) or DDC (digital downconversion) operations inside the FPGA.  If your   baseband signals exceed {-1.0,+1.0}, they are simply clipped into that range.

The hardware designers try to match the largest output of the DAC to the largest IF port signal requirements of the mixers and amplifiers, but that "match" is necessarily   somewhat fluid due to the vagaries of analog hardware operating over large frequency ranges and other operational parameters.  So, the recommendation is to   have your baseband signals not exceed about {-0.9,+0.9} or perhaps somewhat smaller.

Ettus/NI don't provide a "structured walk-through" of their hardware.  But they all follow a similar approach that would be very familiar to any engineer that is somewhat familiar   with RF system design, most SDRs follow a very similar design pattern, regardless of manufacturer.

On the TX path:


computer-software---->interface-to-SDR--->DUC(FPGA)--->DAC--->MIXER--->RF-AMPs---->Antenna-Port
^
|+LO

On the RX path:

Antenna-port-->RF-AMPs--MIXER--->ADC--->DDC---interface-to-SDR---->computer-software
                                              ^
                                               |+LO




You'll find diagrams like that scattered all over Google when you search on terms like "what is an SDR?".






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