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Re: Ettus N210 clock test header


From: Marcus Müller
Subject: Re: Ettus N210 clock test header
Date: Mon, 27 Jun 2022 13:30:35 +0200
User-agent: Mozilla/5.0 (X11; Linux x86_64; rv:91.0) Gecko/20100101 Thunderbird/91.9.0

Hi Fabien,

I bet the usrp-users mailing list would be a better place to ask this!
Anyways, yep, you can. Call the usrp2_clock_ctrl.enable_test_clock() routine. From the top of my head, multi_usrp doesn't expose that directly, but you could easily do, roughly:

0. get the source code of **exactly** the UHD you're using (we don't want to end up having to recompile everything that uses it because we're using even a slightly different ABI). Assuming that's the UHD that came with your linux distro, use `dnf download --source uhd` (for fedoroids), `apt-get source uhd` (for debian, and debianoids like ubuntu)…, and follow the build instructions on how to build local packages (`fedpkg local` on fedora, `debuild -b -uc -us` on debian)

1. find usrp2_impl::usrp2_impl in the source code
2. in the loop going over all motherboards, add something like:
   _mbc[mb].clock.enable(true);
3. build and install (the package, if applicable)

Cheers,
Marcus

PS: instead of hardcoding the clock to be enabled, you can also add a property tree entry like this instead (from the top of my head, didn't even try to type that into anything with syntax checking):

   tree->create<bool>(mb_path / "test_clock" / "enable")
       .set_coercer(
           boost::bind(
               &usrp2_clock_ctrl::enable_test_clock,
               _mbc[mb].clock,
               _1
       ))
       .set(true);

That way, you get a property tree entry that you can set / unset at runtime.


On 27/06/2022 13.03, Fabien PELLET wrote:
Hello,

How can I enable the test clock output on J503 in my USRP N210 ? Is there a way to do that only using UHD methods that I can use in my C++ code ?

I would like to use it on a hardware I'm designing that need to be perfectly synchronised with the internal DAC, ADC and FPGA.

Thanks for the help,

Best regards,

Fabien, F4CTZ.


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