Re: [gforth] Performance anomality with dynamic superinstructions on MIPSel

[David Kuehling]

Replying to myself, quick update (before I have to shutdown my computer
for today):

The instruction in question is 'rdhwr v1,$29' which is mips32r2, i.e.
not supported on Loongson2f.  GCC outputs it via a sequence like:

        .set    push
        .set    mips32r2        
        rdhwr   $3,$29
        .set    pop

I guess on MIPS the GCC runtime nowadays uses model specific register
$29 (which is not CPU reg $29 !) for addressing thread local storage.
To support older mipses this is implemented in kernel via an invalid
opcode interrupt emulation.  I.e. very slow.  How can we prevent writes
to thread local storage from creeping into goto*?

David
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