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Fetch-and-store for PowerPC... and more!

From: Ludovic Courtès
Subject: Fetch-and-store for PowerPC... and more!
Date: Wed, 16 Mar 2005 09:48:08 +0100
User-agent: Gnus/5.1007 (Gnus v5.10.7) Emacs/21.3 (gnu/linux)


Guile 1.7.2 doesn't compile on PowerPC because the `FETCH_STORE' macro
(in `arbiters.c') that is defined is the generic one.  The generic
version of `FETCH_STORE' relies on `scm_mutex_lock ()' and
`scm_mutex_unlock ()' which are not (yet) implemented.

So I implemented the PowerPC-version (32-bit) of `FETCH_STORE' (see
below, this is a well-documented example).  Below is also a tiny test
program that shows that, well, it fetches and stores.  ;-)

After doing it, it occurred to me that maybe I should have look at Glibc
before doing it.  And it turns out that Glibc, indeed, already
implements fetch-and-store for 15 architectures (see `always_swap ()' in
`atomicity.h')...  Unfortunately, this header doesn't seem to get
installed, so we'll have to rip it (G++ also comes with its own
implementation of fetch-and-store among other things anyway).


diff -ubB --show-c-function /home/ludo/tmp/guile-1.7.2/libguile/arbiters.c\~ 
--- /home/ludo/tmp/guile-1.7.2/libguile/arbiters.c~     2004-08-22 
03:49:10.000000000 +0200
+++ /home/ludo/tmp/guile-1.7.2/libguile/arbiters.c      2005-03-16 
09:35:07.000000000 +0100
@@ -36,7 +36,9 @@
    ENHANCE-ME: Add more cpu-specifics.  glibc atomicity.h has some of the
    sort of thing required.  FETCH_STORE could become some sort of
-   compare-and-store if that better suited what various cpus do.  */
+   compare-and-store if that better suited what various cpus do.  Note: look
+   at the `always_swap ()' function is Glibc's `atomicity.h' in the `sysdeps'
+   directory.  */
 #if defined (__GNUC__) && defined (i386) && SIZEOF_SCM_T_BITS == 4
 /* This is for i386 with the normal 32-bit scm_t_bits.  The xchg instruction
@@ -59,6 +61,28 @@
   } while (0)
+#if defined (__GNUC__) && defined (__powerpc__) && SIZEOF_SCM_T_BITS == 4
+/* On 32-bit PowerPC arches, we use the `lwarx' ("load word and reserve,
+   indexed") and `stwcx.' ("store word conditional, indexed") instructions.
+   In effect, data is loaded from MEM into FET and a reservation bit is set
+   to 1; `stwcx.' will only store STO into MEM if the reservation bit is
+   still set when it is executed, otherwise we start again the whole process.
+   This is a well-known example available in the "PowerPC Processor Reference
+   Guide" by Xilinx, for example.  */
+#define FETCH_STORE(fet,mem,sto)               \
+do {                                           \
+  asm ("\n1:\n"                                        \
+       "\tlwarx %0,0,%1\n"                     \
+       "\tstwcx. %2,0,%1\n"                    \
+       "\tbne- 1b\n"                           \
+       : "=&r" (fet)                           \
+       : "r" (mem), "r" (sto));                        \
+} while (0)
 #ifndef FETCH_STORE
 /* This is a generic version, with a mutex to ensure the operation is
    atomic.  Unfortunately this approach probably makes arbiters no faster

#include <stdio.h>
#include <assert.h>

#define FETCH_STORE(fet,mem,sto)                \
do {                                            \
  asm ("\n1:\n"                                 \
       "\tlwarx %0,0,%1\n"                      \
       "\tstwcx. %2,0,%1\n"                     \
       "\tbne- 1b\n"                            \
       : "=&r" (fet)                            \
       : "r" (mem), "r" (sto));                 \
} while (0)

static int in_memory = 12;

main (int argc, char *argv[])
  int old_value = 0, new_value = 7;

  while (1)
      int actual_old_value = in_memory;
      FETCH_STORE (old_value, &in_memory, new_value);

      printf ("old=%i, new=%i, mem=%i\n", old_value, new_value, in_memory);
      assert (old_value == actual_old_value);
      assert (new_value == in_memory);
      new_value += old_value;

  return 0;

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