bug#46069: [PATCH] gnu: Add Verilator.

[Nicolas Goaziou]

Hello,

Andrew Miloradovsky <andrew@interpretmath.pw> writes:

> * gnu/packages/fpga.scm (verilator): New variable.

I added a copyright line for you in "fpga.scm" and applied your patch
with the changes detailed below.

> +    (source (origin
> +              (method url-fetch)
> +              (uri (string-append
> +                    "https://github.com/"; name "/"
> +                    name "/archive/v" version ".tar.gz"))

This is an unstable release, so I used git-fetch instead, with the tag
corresponding to the release.

> +    (native-inputs `(("autoconf" ,autoconf)
> +                     ("automake" ,automake)
> +                     ("gettext" ,gettext-minimal)
> +                     ("perl" ,perl)
> +                     ("python" ,python)
> +                     ("flex" ,flex)
> +                     ("bison" ,bison)
> +                     ("systemc" ,systemc)))

I re-ordered native-inputs alphabetically, and moved perl and systemc to
regular inputs instead. I'm not absolutely sure about this change, but
it still compiles. Let me know if this is not appropriate.

> +    (synopsis "A fast Verilog/SystemVerilog simulator")

I tweaked the synopsis so it doesn't start with the "A" article. Running
"guix lint" should warn you about it.

> +    (description "It compiles SystemVerilog to C++ or SystemC.
> +The user writes a little C++/SystemC wrapper file, which instantiates the
> +'Verilated' model of the user’s top level module.  These C++/SystemC files 
> are
> +then compiled by a C++ compiler (GCC/Clang/etc.).  The resulting executable
> +performs the design simulation.  Verilator also supports linking its 
> generated
> +libraries, optionally encrypted, into other simulators.")

I slightly reworded the beginning of the description according to
information from the GitHub repository.

Thank you.

Regards,
-- 
Nicolas Goaziou