question: how to automatically define a group of variables

[Resnick, David]

I'm struggling to simplify a Makefile that is getting cluttered up with
repetition every time we add support for a new language.  We have
sets of statements like the following:

*************************************************
NONBI_SRCS_FRFR = lang-kernel.frfr.c lang-util.c
NONBI_SRCS_DEDE = lang-kernel.dede.c lang-util.c
NONBI_SRCS_ITIT = lang-kernel.itit.c lang-util.c
NONBI_SRCS_PTBR = lang-kernel.ptbr.c lang-util.c
NONBI_SRCS_ESCL = lang-kernel.escl.c lang-util.c

tdb%-bi.c: $(NONBI_SRCS_%:.c=.o)
*************************************************

I originally naively thought I could do something like the following
(disregarding the
upper/lower case issue for now):

*************************************************
define newline

endef
lc_ccs = frfr dede itit ptbr escl
$(foreach lccc, $(lc_ccs), NONBI_SRCS_$(lccc) = lang-kernel.$(lccc).c
lang-util.c $(newline))
*************************************************

Alas, that results in a '*** missing separator.  Stop.' error.  What I want
for it to do is
to expand, e.g., to:
NONBI_SRCS_frfr = lang-kernel.frfr.c lang-util.c
before Make decides that the line doesn't have a form like var = defn or
TARGETS: blah blah blah.

I pawed through the info file for some time, and asked the local Make
experts, but couldn't come
up with a satisfactory answer.  Any help on how to do this (or a pointer to
where I might find
the answer) would be greatly appreciated.  If it is relevant, we're running
make-3.79.1.

Thanks,
-David

address@hidden