Computing variable names inside pattern rules?

[Andrew Church]

     I'm using GNU make 3.79.1 and trying to write a pattern rule in a
Makefile that will use the contents of a variable whose name depends on the
target as prerequisites.  For example, I have a Makefile that defines:

MODULES = main.so access.so
OBJECTS-main.so = collide.so set.o util.o
include ../Makerules

and a "Makerules" file which says, among other things:

%.so: %.o $(OBJECTS-%.so)
        $(CC) -shared $^ -o $@
%.a: %.o $(OBJECTS-%.so)
        ar r $@ $^

However, make does not seem to insert the target stem into the variable
name, so main.so and main.a end up with only main.o as a prerequisite.  The
documentation suggests that this occurs because variables in prerequisites
are expanded before the rules themselves are checked.

     Is there another way to accomplish the above within make, or will I
have to resort to shell kludges or restructure the compilation process?

     Any help would be appreciated.  Thanks in advance.

  --Andrew Church
    address@hidden
    http://achurch.org/