using "include" in a Makefile

[VSong]

System: cygwin
Make Version: 3.79.1

Hi,

I'm trying to include a makefile by using "include", but it doesn't seem to
be working.  I'll set up an example of what I'm trying todo (simplified):

>>>>>> Start Example >>>>>>
Makefile
==========
#Make file for ProgramA

ProgramA: FileA.cs
<TAB>csc /debug /t:library /out:bin/Debug/address@hidden $^


Makefile
==========
#Makefile for ProgramB

include ../ProgramA/Makefile

ProgramB: FileB.cs
<TAB>csc /debug /t:library /out:bin/Debug/address@hidden $^

This generates the following error ('make' in ProgramB):
=======================
cd ~/ProgramB/
make -k
make: *** No rule to make target `FileA.cs', needed by `ProgramA'.
csc /debug /t:library /out:bin/Debug/ProgramA.dll FileA.cs

<<<< End Example <<<<<

I can get it work if I change directory explicitly and 'make'. (i.e. cd
../ProgramA; make)

Doesn't 'include' just change directory and run 'make'?

Thanks.
Victor