Re: evaluated target specific variable

[Paul D. Smith]

%% andre maute <address@hidden> writes:

  am> consider the following Makefile, working under linux, make 3.80

  am> ------------------------------
  am> test2: OBJECTS=$(shell ls a.o)
  am> test2: $(shell ls a.o)
  am> test2: $(OBJECTS)
  am>         echo $(OBJECTS)
  am>         touch test2
  am> -------------------------------

  am> the following commands

  am> # > touch a.o
  am> # > make
  am> # > make
  am> # > touch a.o
  am> # > make

  am> the first and third time make is issued the echo happens, well
  am> that's the intended behaviour. If you remove the second test2
  am> target, only the first make will issue the echo, why?

>From the GNU make manual, section "Target-Specific Variable Values",
second paragraph:

     The other exception is "target-specific variable values".  This
  feature allows you to define different values for the same variable,
  based on the target that `make' is currently building.  As with
  automatic variables, these values are only available within the context
  of a target's command script (and in other target-specific assignments).

Note the last sentence here: the value of $(OBJECTS) is empty when used
as a prerequisite, because the target-specific value only takes effect
within the command script.

-- 
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