Debugging Make

[Ken Smith]

While debugging make files, I have frequently thought it might be nice 
to see what the files contain after make processes them.  In particular, 
I would like to see what the rules and variables look like.  Here is an 
example of a situation where I think this would be useful.

---BEGIN---makefile
$(SOMEPREFIX)%.new : %.in

include anotherfile.mk
---END---makefile

---BEGIN---anotherfile.mk
SOMEPREFIX = prefix
---END---anotherfile.mk

When make runs, we'll have this for the definition of the pattern rule.

---BEGIN---makefile.out
%.new : %.in
---END---makefile.out

If we had included anotherfile.mk at the top of makefile, we would 
instead have this.
---BEGIN---makefile.out
prefix%.new : %.in
---END---makefile.out

Sometimes, errors like this are hard to detect.  I would like to be able 
to run my makefiles through some processor (make -someflag > 
makefile.out) and see what make thinks I'm telling it.  here's more 
straightforward example.

---BEGIN---makefile
a=target
b=$(a)
c=$(b)
target=hi
d=$($(c))
---END---makefile

After running through the debugging feature I'm talking about, 
makefile.out would contain the following.

---BEGIN---makefile.out
a=target
b=target
c=target
target=hi
d=hi
---END---makefile.out

Does something like this already exist?  If it doesn't could it be added 
to GNU make?

Ken Smith