make expansion?

[Sebastien Mirolo]

Hi,

I was wondering if there is an option to get the expanded version of a 
Makefile as when you get expansion of macros with gcc -E ?

For example, if my Makefile is:
SRC=foo.c
OBJ=foo.o

$(OBJ): $(SRC)
      gcc -c -o $(OBJ) $(SRC)

"make -E" would print:

foo.o: foo.c
    gcc -c -o foo.o foo.c

I've tried 'make -p' and 'make -d', but none of them are actually giving me 
the output I am looking for. Is there any solution?

Thank you,
Sebastien.