include'ing a Makefile twice ?

[Frazer Worley]

My Makefile is divided into 2 pieces. The man "flow" Makefile - controlled by me the flow owner, and 
the "project" Makefile controlled by the user which includes the "flow" Makefile and allows the user 
to make project specific flow customizations

Makefile (project)
  + synth.mk (flow)

Now, the flow Makefile outlines a process

  STEP1, STEP2, ... STEP N

such that generally each STEP depends on the result of the previous.

  ie. STEP3 depends upon STEP2 result

Some users however may wish to alter these default dependencies such that perhaps:

  STEP3 depends on the STEP1 result.

I have a target for each step:

eg. from synth.mk

...

${STEP3_PREREQUISITES}= ${STEP2_RESULT}

${STEP3_RESULT}: ${STEP3_PREREQUISITES}
  commands

The user would change the dependency relationship in the project Makefile thus

include synth.mk

${STEP3_PREREQUISITES}:= ${STEP1_RESULT}

However this doesn't work. If I include synth.mk after the redefinition of  ${STEP3_PREREQUISITES} thus:

include synth.mk

${STEP3_PREREQUISITES}:= ${STEP1_RESULT}

include synth.mk

I guess the functionality I want - but incur other side effects as a result of the Makefile being include twice.

Is there a way to force the Makefile to re-evaluate the variables and dependencies ? 

I realize I can break the Makefile into 3 pieces, project, flow targets, flow definitions but I'd rather keep the 
format as it is. I could also restart the STEP1 variables in the project Makefile and get it to work - but I'd 
rather not have them in two places ... and they belong in the flow Makefile has they are common to many
users / projects.

So I need:

include Makefile which defines variables and targets
redefined variables
re-evaluate dependencies

Thanks,

-Frazer