Re: Skipped secondary expansions inside make rules

[Paul Smith]

On Mon, 2011-03-07 at 04:53 +0300, Dmitry N. Mikushin wrote:
> > Why did you use $$?
> 
> Well, I think because my understanding of $$ is poor. From manual I
> understood $$ should be issued in cases when we want to evaluate a
> variable whose name is constructed from other tokens. Why it is not
> the case here?

That's not really what $$ is for.  $$ is, very simply, escaping the "$"
so that make does not expand the value.

What is happening is that at various points in a makefile content may be
expanded more than one time.  In those situations you have to think
about whether you want variables/functions to be expanded the first time
through, or the second time.  If the latter, you have to escape the "$"
so the first expansion doesn't interpret it and the second one will.

In order to understand when you need $ and when you need $$ you need to
understand expansion, when it happens, and why you might want to defer
it until next time.

Typically the only time you need to worry about this is when (a) you're
using $(call ...) and sometimes $(eval ...), or (b) when you're using
secondary expansion targets.

You're not using either here.

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