Re: [lwip-users] Problem running lwip on cortex M7 with D cache enabled

[goldsimon]

Jochen Strohbeck wrote:
>I'm using lwip 1.4.1 and FreeRTOS on a SAME70 custom board with success
>if D-cache is disabled. If I enable the D-cache no more packets are
>received. If I place the RX descriptor into a non-cacheable region I
>get
>packets again

No surprises so far ;-)

> but the received data is corrupt.
> [..]
> I guess this is due to the
>D-cache requirements that the (GMAC) DMA buffer must be aligned to
>32bytes

I don't know that MAC yet, but does it really require this alignment? Whatever, 
you'll need this requirement to ensure cache flushes don't interfere with 
adjacent data. In other words, you need tx/rx pbufs where struct pbuf and it's 
payload don't share a cache line.

I have no short fix for this at hand. Sorry. You could try to create headroom 
in the pbuf to separate struct and data a bit, but this is only an idea...

We still have a task open to work on fully supporting zero copy tx/rx.

Supporting this on the stm boards would be interesting, too.

Aside from this, don't stick with Atmel's old version of lwip. You'll get many 
bugs that are already fixed, including some security related ;-)

Simon