paparazzi-devel
[Top][All Lists]
Advanced

[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]

RE: [Paparazzi-devel] MeekPE PPM Decoder


From: Luke
Subject: RE: [Paparazzi-devel] MeekPE PPM Decoder
Date: Thu, 23 Sep 2010 21:52:14 -0700

Michel,

Thank you very much for your swift help. In fact there were no errors returned for either the top or bottom solder masks. Presumably they are not as strict with the mask as with the copper traces themselves.  

It seems to me one could dispense with all text on the copper and mask layers, and use only the silk/print layers for text. I don’t know about other fab houses, but BatchPCB allows silk/printing on both top AND bottom at no additional charge. This would be .GTO and .GBO.

 

As for board outline, of course this can be either on the copper layer or the silk layer, it makes no difference.

 

However I am happy with whatever you decide, you are doing me the favor!


Luke

 

 

 


From: address@hidden [mailto:address@hidden On Behalf Of Michel GORRAZ
Sent: Thursday, September 23, 2010 9:38 PM
To: address@hidden
Subject: Re: [Paparazzi-devel] MeekPE PPM Decoder

 

Last question : did you get some error with text on Bottom Solder Mask ( .GBS ) ?

@+
Michel

2010/9/24 Michel GORRAZ <address@hidden>

Ok, i see, violations are only because of copper text: letter/letter and text/border spacing.
Drill format issue is also easy to correct: i will discard the optimizing change location option on my Gerber file generator.
I'll release a "BatchPCB compliant" version as fast as possible...

@+


Michel

2010/9/23 Luke <address@hidden>

Michel, thank you very much for the reply.

 

I don’t know if attachments are allowed to be sent to this list but I am trying to attach an image showing the problem parts of GTL and GBL (highlighted in Pink). Yes, the border is also an issue since apparently it is not spaced beyond 8 mil from some of the pads (on the top layer) or from the ground plane (on the bottom layer). At least this is what their DRC believes – I have not measured it with a ruler or anything ;)

You are right about the drill file, it is mostly just adding redundant Y information. I have attached the modified file (.DRL). This is the specification I used:
http://tinyurl.com/2ef2fjr

 

If making these changes is too much work don’t worry about it, I can recreate the design in Eagle myself. But if it is easy I thought it would not hurt to ask! I could also ask BatchPCB if they will relax their DRC rules for text, in the manner of Olimex. Some boards can be passed manually even if they do not meet the automatic DRC.


Luke

 

 

 


From: paparazzi-devel-bounces+lukez=kualumni.org@nongnu.org [mailto:paparazzi-devel-bounces+lukez=kualumni.org@nongnu.org] On Behalf Of Michel GORRAZ
Sent: Thursday, September 23, 2010 1:26 PM
To: address@hidden
Subject: Re: [Paparazzi-devel] MeekPE PPM Decoder

 

Hi Luke,

If i understand correctly, you want me to remove writing on top and bottom copper layer, right ?
But why did you also remove the border ? (border lines are 8mil !?!)
What did you change exactly in the drill file ? (you added some missing redundant X or Y coordinates, right ?)
GTL and GBL (and all other layers) where already generated with minimum 8 mil spacing, it's the minimum trace and space requirement of my favorite PCB fab house (Olimex),
but they allow less than 8mil only for writing.
I'm not volunteer to use Eagle, no way :)

Regards
Michel

2010/9/23 Luke <address@hidden>

Hi Guys,

I just noticed that under “Other Hardware” on the wiki a new PPM encoder board has been posted, called MeekPE. It does not use a microcontroller and is a very neat design.

I don’t want to create more work for anyone, but I have a relatively simple modification request if Michel would be willing. I would like to have a few boards run off by BatchPCB which is a cheap PCB fab house. Unfortunately the boards do no meet the design requirements, since some traces have less than 8 mil trace spacing.

If the border and the writing were removed from the top and bottom copper layers, this would solve the problem entirely (.GTL and .GBL files respectively). These aren’t electrically necessary traces so it would not change the design at all. The important writing is already also reproduced on the Top Silk layer so it would still be visible to the user.

The other thing BatchPCB requires is for the drill file to be in a different format, but I was able to convert Michel’s drill file already by hand.

This is such a simple design it would be great to have it in Eagle. But maybe that will take some kindly volunteer… ;)

In the meantime, if the GTL and GBL layers could be re-generated with minimum 8 mil spacing, that would allow us to have boards made for very little ($2.50 US)


Luke


_______________________________________________
Paparazzi-devel mailing list
address@hidden
http://lists.nongnu.org/mailman/listinfo/paparazzi-devel

 


_______________________________________________
Paparazzi-devel mailing list
address@hidden
http://lists.nongnu.org/mailman/listinfo/paparazzi-devel

 

 


reply via email to

[Prev in Thread] Current Thread [Next in Thread]