Re: [PATCH v2 02/24] target/arm: Add ALIGN_MEM to TBFLAG_ANY

[Peter Maydell]

On Tue, 8 Dec 2020 at 18:01, Richard Henderson
<richard.henderson@linaro.org> wrote:
>
> Use this to signal when memory access alignment is required.
> This value comes from the CCR register for M-profile, and
> from the SCTLR register for A-profile.
>
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
> ---
>  target/arm/cpu.h       | 20 +++++++++++---------
>  target/arm/translate.h |  2 ++
>  target/arm/helper.c    | 19 +++++++++++++++++--
>  target/arm/translate.c |  7 +++----
>  4 files changed, 33 insertions(+), 15 deletions(-)
>
> diff --git a/target/arm/cpu.h b/target/arm/cpu.h
> index e5514c8286..e074055a94 100644
> --- a/target/arm/cpu.h
> +++ b/target/arm/cpu.h
> @@ -3220,15 +3220,15 @@ typedef ARMCPU ArchCPU;
>   * We put flags which are shared between 32 and 64 bit mode at the top
>   * of the word, and flags which apply to only one mode at the bottom.
>   *
> - *  31          20    18    14          9              0
> - * +--------------+-----+-----+----------+--------------+
> - * |              |     |   TBFLAG_A32   |              |
> - * |              |     +-----+----------+  TBFLAG_AM32 |
> - * |  TBFLAG_ANY  |           |TBFLAG_M32|              |
> - * |              +-----------+----------+--------------|
> - * |              |            TBFLAG_A64               |
> - * +--------------+-------------------------------------+
> - *  31          20                                     0
> + *  31          19  18    14          9              0
> + * +--------------+---+-----+----------+--------------+
> + * |              |   |   TBFLAG_A32   |              |
> + * |              |   +-----+----------+  TBFLAG_AM32 |
> + * |  TBFLAG_ANY  |         |TBFLAG_M32|              |
> + * |              +---------+----------+--------------|
> + * |              |          TBFLAG_A64               |
> + * +--------------+-----------------------------------+
> + *  31          19                                   0
>   *
>   * Unless otherwise noted, these bits are cached in env->hflags.
>   */
> @@ -3241,6 +3241,8 @@ FIELD(TBFLAG_ANY, MMUIDX, 24, 4)
>  FIELD(TBFLAG_ANY, FPEXC_EL, 22, 2)
>  /* For A-profile only, target EL for debug exceptions.  */
>  FIELD(TBFLAG_ANY, DEBUG_TARGET_EL, 20, 2)
> +/* Memory operations require alignment: SCTLR_ELx.A or CCR.UNALIGN_TRP */
> +FIELD(TBFLAG_ANY, ALIGN_MEM, 19, 1)

This is trying to use the same bit as TBFLAG_A64 MTE0_ACTIVE...
We might have to finally start in on using bits in cs_base.

thanks
-- PMM