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[PATCH 2/4] target/arm: Optimize MVE logic ops
From: |
Peter Maydell |
Subject: |
[PATCH 2/4] target/arm: Optimize MVE logic ops |
Date: |
Thu, 2 Sep 2021 16:09:08 +0100 |
When not predicating, implement the MVE bitwise logical insns
directly using TCG vector operations.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
target/arm/translate-mve.c | 41 ++++++++++++++++++++++++--------------
1 file changed, 26 insertions(+), 15 deletions(-)
diff --git a/target/arm/translate-mve.c b/target/arm/translate-mve.c
index d95807541b1..087d60f0d81 100644
--- a/target/arm/translate-mve.c
+++ b/target/arm/translate-mve.c
@@ -774,7 +774,8 @@ static bool trans_VNEG_fp(DisasContext *s, arg_1op *a)
return do_1op(s, a, fns[a->size]);
}
-static bool do_2op(DisasContext *s, arg_2op *a, MVEGenTwoOpFn fn)
+static bool do_2op_vec(DisasContext *s, arg_2op *a, MVEGenTwoOpFn fn,
+ GVecGen3Fn *vecfn)
{
TCGv_ptr qd, qn, qm;
@@ -787,28 +788,38 @@ static bool do_2op(DisasContext *s, arg_2op *a,
MVEGenTwoOpFn fn)
return true;
}
- qd = mve_qreg_ptr(a->qd);
- qn = mve_qreg_ptr(a->qn);
- qm = mve_qreg_ptr(a->qm);
- fn(cpu_env, qd, qn, qm);
- tcg_temp_free_ptr(qd);
- tcg_temp_free_ptr(qn);
- tcg_temp_free_ptr(qm);
+ if (vecfn && s->mve_no_pred) {
+ vecfn(a->size, mve_qreg_offset(a->qd), mve_qreg_offset(a->qn),
+ mve_qreg_offset(a->qm), 16, 16);
+ } else {
+ qd = mve_qreg_ptr(a->qd);
+ qn = mve_qreg_ptr(a->qn);
+ qm = mve_qreg_ptr(a->qm);
+ fn(cpu_env, qd, qn, qm);
+ tcg_temp_free_ptr(qd);
+ tcg_temp_free_ptr(qn);
+ tcg_temp_free_ptr(qm);
+ }
mve_update_eci(s);
return true;
}
-#define DO_LOGIC(INSN, HELPER) \
+static bool do_2op(DisasContext *s, arg_2op *a, MVEGenTwoOpFn *fn)
+{
+ return do_2op_vec(s, a, fn, NULL);
+}
+
+#define DO_LOGIC(INSN, HELPER, VECFN) \
static bool trans_##INSN(DisasContext *s, arg_2op *a) \
{ \
- return do_2op(s, a, HELPER); \
+ return do_2op_vec(s, a, HELPER, VECFN); \
}
-DO_LOGIC(VAND, gen_helper_mve_vand)
-DO_LOGIC(VBIC, gen_helper_mve_vbic)
-DO_LOGIC(VORR, gen_helper_mve_vorr)
-DO_LOGIC(VORN, gen_helper_mve_vorn)
-DO_LOGIC(VEOR, gen_helper_mve_veor)
+DO_LOGIC(VAND, gen_helper_mve_vand, tcg_gen_gvec_and)
+DO_LOGIC(VBIC, gen_helper_mve_vbic, tcg_gen_gvec_andc)
+DO_LOGIC(VORR, gen_helper_mve_vorr, tcg_gen_gvec_or)
+DO_LOGIC(VORN, gen_helper_mve_vorn, tcg_gen_gvec_orc)
+DO_LOGIC(VEOR, gen_helper_mve_veor, tcg_gen_gvec_xor)
static bool trans_VPSEL(DisasContext *s, arg_2op *a)
{
--
2.20.1