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[PATCH v3 4/6] target/arm: Assert thumb pc is aligned
From: |
Richard Henderson |
Subject: |
[PATCH v3 4/6] target/arm: Assert thumb pc is aligned |
Date: |
Sun, 19 Sep 2021 19:45:02 -0700 |
Misaligned thumb PC is architecturally impossible.
Assert is better than proceeding, in case we've missed
something somewhere.
Expand a comment about aligning the pc in gdbstub.
Fail an incoming migrate if a thumb pc is misaligned.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/arm/gdbstub.c | 9 +++++++--
target/arm/machine.c | 9 +++++++++
target/arm/translate.c | 3 +++
3 files changed, 19 insertions(+), 2 deletions(-)
diff --git a/target/arm/gdbstub.c b/target/arm/gdbstub.c
index 826601b341..a54b42418b 100644
--- a/target/arm/gdbstub.c
+++ b/target/arm/gdbstub.c
@@ -76,8 +76,13 @@ int arm_cpu_gdb_write_register(CPUState *cs, uint8_t
*mem_buf, int n)
tmp = ldl_p(mem_buf);
- /* Mask out low bit of PC to workaround gdb bugs. This will probably
- cause problems if we ever implement the Jazelle DBX extensions. */
+ /*
+ * Mask out low bits of PC to workaround gdb bugs.
+ * This avoids an assert in thumb_tr_translate_insn, because it is
+ * architecturally impossible to misalign the pc.
+ * This will probably cause problems if we ever implement the
+ * Jazelle DBX extensions.
+ */
if (n == 15) {
tmp &= ~1;
}
diff --git a/target/arm/machine.c b/target/arm/machine.c
index 81e30de824..b5004a67e9 100644
--- a/target/arm/machine.c
+++ b/target/arm/machine.c
@@ -781,6 +781,15 @@ static int cpu_post_load(void *opaque, int version_id)
hw_breakpoint_update_all(cpu);
hw_watchpoint_update_all(cpu);
+ /*
+ * Misaligned thumb pc is architecturally impossible.
+ * We have an assert in thumb_tr_translate_insn to verify this.
+ * Fail an incoming migrate to avoid this assert.
+ */
+ if (!is_a64(env) && env->thumb && (env->regs[15] & 1)) {
+ return -1;
+ }
+
if (!kvm_enabled()) {
pmu_op_finish(&cpu->env);
}
diff --git a/target/arm/translate.c b/target/arm/translate.c
index 62c396b880..e522cd2fbe 100644
--- a/target/arm/translate.c
+++ b/target/arm/translate.c
@@ -9640,6 +9640,9 @@ static void thumb_tr_translate_insn(DisasContextBase
*dcbase, CPUState *cpu)
uint32_t insn;
bool is_16bit;
+ /* Misaligned thumb PC is architecturally impossible. */
+ assert((dc->base.pc_next & 1) == 0);
+
if (arm_check_ss_active(dc) || arm_check_kernelpage(dc)) {
dc->base.pc_next += 2;
return;
--
2.25.1
- [PATCH v3 0/6] target/arm: Fix insn exception priorities, Richard Henderson, 2021/09/19
- [PATCH v3 2/6] linux-user/arm: Report SIGBUS and SIGSEGV correctly, Richard Henderson, 2021/09/19
- [PATCH v3 1/6] linux-user/aarch64: Handle EC_PCALIGNMENT, Richard Henderson, 2021/09/19
- [PATCH v3 4/6] target/arm: Assert thumb pc is aligned,
Richard Henderson <=
- [PATCH v3 6/6] tests/tcg: Add arm and aarch64 pc alignment tests, Richard Henderson, 2021/09/19
- [PATCH v3 3/6] target/arm: Take an exception if PC is misaligned, Richard Henderson, 2021/09/19
- [PATCH v3 5/6] target/arm: Suppress bp for exceptions with more priority, Richard Henderson, 2021/09/19