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[PATCH v6 14/24] target/arm: Enable SCR and HCR bits for RAS
From: |
Richard Henderson |
Subject: |
[PATCH v6 14/24] target/arm: Enable SCR and HCR bits for RAS |
Date: |
Fri, 6 May 2022 13:02:32 -0500 |
Enable writes to the TERR and TEA bits when RAS is enabled.
These bits are otherwise RES0.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/arm/helper.c | 9 +++++++++
1 file changed, 9 insertions(+)
diff --git a/target/arm/helper.c b/target/arm/helper.c
index 37c5e42bc0..b6faebf4a7 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -1755,6 +1755,9 @@ static void scr_write(CPUARMState *env, const
ARMCPRegInfo *ri, uint64_t value)
}
valid_mask &= ~SCR_NET;
+ if (cpu_isar_feature(aa64_ras, cpu)) {
+ valid_mask |= SCR_TERR;
+ }
if (cpu_isar_feature(aa64_lor, cpu)) {
valid_mask |= SCR_TLOR;
}
@@ -1769,6 +1772,9 @@ static void scr_write(CPUARMState *env, const
ARMCPRegInfo *ri, uint64_t value)
}
} else {
valid_mask &= ~(SCR_RW | SCR_ST);
+ if (cpu_isar_feature(aa32_ras, cpu)) {
+ valid_mask |= SCR_TERR;
+ }
}
if (!arm_feature(env, ARM_FEATURE_EL2)) {
@@ -5126,6 +5132,9 @@ static void do_hcr_write(CPUARMState *env, uint64_t
value, uint64_t valid_mask)
if (cpu_isar_feature(aa64_vh, cpu)) {
valid_mask |= HCR_E2H;
}
+ if (cpu_isar_feature(aa64_ras, cpu)) {
+ valid_mask |= HCR_TERR | HCR_TEA;
+ }
if (cpu_isar_feature(aa64_lor, cpu)) {
valid_mask |= HCR_TLOR;
}
--
2.34.1
- [PATCH v6 06/24] target/arm: Update qemu-system-arm -cpu max to cortex-a57, (continued)
- [PATCH v6 06/24] target/arm: Update qemu-system-arm -cpu max to cortex-a57, Richard Henderson, 2022/05/06
- [PATCH v6 07/24] target/arm: Set ID_DFR0.PerfMon for qemu-system-arm -cpu max, Richard Henderson, 2022/05/06
- [PATCH v6 08/24] target/arm: Split out aa32_max_features, Richard Henderson, 2022/05/06
- [PATCH v6 09/24] target/arm: Annotate arm_max_initfn with FEAT identifiers, Richard Henderson, 2022/05/06
- [PATCH v6 10/24] target/arm: Use field names for manipulating EL2 and EL3 modes, Richard Henderson, 2022/05/06
- [PATCH v6 11/24] target/arm: Enable FEAT_Debugv8p2 for -cpu max, Richard Henderson, 2022/05/06
- [PATCH v6 12/24] target/arm: Enable FEAT_Debugv8p4 for -cpu max, Richard Henderson, 2022/05/06
- [PATCH v6 13/24] target/arm: Add minimal RAS registers, Richard Henderson, 2022/05/06
- [PATCH v6 17/24] target/arm: Enable FEAT_RAS for -cpu max, Richard Henderson, 2022/05/06
- [PATCH v6 15/24] target/arm: Implement virtual SError exceptions, Richard Henderson, 2022/05/06
- [PATCH v6 14/24] target/arm: Enable SCR and HCR bits for RAS,
Richard Henderson <=
- [PATCH v6 19/24] target/arm: Enable FEAT_CSV2 for -cpu max, Richard Henderson, 2022/05/06
- [PATCH v6 21/24] target/arm: Enable FEAT_CSV3 for -cpu max, Richard Henderson, 2022/05/06
- [PATCH v6 18/24] target/arm: Enable FEAT_IESB for -cpu max, Richard Henderson, 2022/05/06
- [PATCH v6 16/24] target/arm: Implement ESB instruction, Richard Henderson, 2022/05/06
- [PATCH v6 20/24] target/arm: Enable FEAT_CSV2_2 for -cpu max, Richard Henderson, 2022/05/06
- [PATCH v6 24/24] target/arm: Define neoverse-n1, Richard Henderson, 2022/05/06
- [PATCH v6 23/24] target/arm: Define cortex-a76, Richard Henderson, 2022/05/06
- [PATCH v6 22/24] target/arm: Enable FEAT_DGH for -cpu max, Richard Henderson, 2022/05/06
- Re: [PATCH v6 00/24] target/arm: Cleanups, new features, new cpus, Peter Maydell, 2022/05/09