Re: [PATCH v5 02/20] target/arm: ensure TCG IO accesses set appropriate MemTxAttrs

[Richard Henderson]

On 11/12/22 04:25, Alex Bennée wrote:
> diff --git a/target/arm/ptw.c b/target/arm/ptw.c
> index 3745ac9723..4b6683f90d 100644
> --- a/target/arm/ptw.c
> +++ b/target/arm/ptw.c
> @@ -2634,6 +2634,7 @@ static bool get_phys_addr_twostage(CPUARMState *env, 
> S1Translate *ptw,
>       s1_lgpgsz = result->f.lg_page_size;
>       cacheattrs1 = result->cacheattrs;
>       memset(result, 0, sizeof(*result));
> +    result->f.attrs = MEMTXATTRS_CPU(env_cpu(env));

Ouch.  This means that f.secure has been reset too, which would break Secure EL1 running 
under Secure EL2.  I'll prepare a fix for 7.2...

Anyway,
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>


r~

>   
>       ret = get_phys_addr_lpae(env, ptw, ipa, access_type, is_el0, result, fi);
>       fi->s2addr = ipa;
> @@ -2872,7 +2873,7 @@ hwaddr arm_cpu_get_phys_page_attrs_debug(CPUState *cs, 
> vaddr addr,
>           .in_secure = arm_is_secure(env),
>           .in_debug = true,
>       };
> -    GetPhysAddrResult res = {};
> +    GetPhysAddrResult res = { .f.attrs = MEMTXATTRS_CPU(cs) };
>       ARMMMUFaultInfo fi = {};
>       bool ret;
>   
> diff --git a/target/arm/tlb_helper.c b/target/arm/tlb_helper.c
> index 0f4f4fc809..5960269421 100644
> --- a/target/arm/tlb_helper.c
> +++ b/target/arm/tlb_helper.c
> @@ -208,7 +208,7 @@ bool arm_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
>                         bool probe, uintptr_t retaddr)
>   {
>       ARMCPU *cpu = ARM_CPU(cs);
> -    GetPhysAddrResult res = {};
> +    GetPhysAddrResult res = { .f.attrs = MEMTXATTRS_CPU(cs) };
>       ARMMMUFaultInfo local_fi, *fi;
>       int ret;
>