After submitting a patch for cortex-a55 support and trying to run SMP on odroid-c4 I have found concern about mpidr_el1 register.
cortex-a55 (and also a75/76/78) seem to be considered SMT CPUs with single SMT thread. As a result,
they publish core numbers in AFF1 rather than in AFF0 and AFF0 is always zero. In the cortex-a55 TRM:
Aff1, [11:8] Part of Affinity level 1. Third highest level affinity field.
CPUID. Identification number for each CPU in the Cortex-A55 cluster:
0x0 MP1: CPUID: 0. to
0x7 MP8: CPUID: 7.
Aff0, [7:0]
Affinity level 0. The level identifies individual threads within a multi-threaded core. The
Cortex-A55 core is single-threaded, so this field has the value 0x00.
Plus MT (bit 24) is set to 1.
But it seems that qemu does not take it into account. Is this intentional? Does it make sense to change this behaviour to something closer to
real CPU ?