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[PATCH v4 02/30] hw/mips/malta: Set PIIX4 IRQ routes in embedded bootloa
From: |
Bernhard Beschow |
Subject: |
[PATCH v4 02/30] hw/mips/malta: Set PIIX4 IRQ routes in embedded bootloader |
Date: |
Wed, 21 Dec 2022 17:59:35 +0100 |
From: Philippe Mathieu-Daudé <philmd@linaro.org>
Linux kernel expects the northbridge & southbridge chipsets
configured by the BIOS firmware. We emulate that by writing
a tiny bootloader code in write_bootloader().
Upon introduction in commit 5c2b87e34d ("PIIX4 support"),
the PIIX4 configuration space included values specific to
the Malta board.
Set the Malta-specific IRQ routing values in the embedded
bootloader, so the next commit can remove the Malta specific
bits from the PIIX4 PCI-ISA bridge and make it generic
(matching the real hardware).
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Message-Id: <20221027204720.33611-3-philmd@linaro.org>
---
hw/mips/malta.c | 19 +++++++++++++++++++
1 file changed, 19 insertions(+)
diff --git a/hw/mips/malta.c b/hw/mips/malta.c
index 2e175741ff..ef3e10dc4d 100644
--- a/hw/mips/malta.c
+++ b/hw/mips/malta.c
@@ -804,6 +804,8 @@ static void write_bootloader_nanomips(uint8_t *base,
uint64_t run_addr,
stw_p(p++, 0x8422); stw_p(p++, 0x9088);
/* sw t0, 0x88(t1) */
+ /* TODO set PIIX IRQC[A:D] routing values! */
+
stw_p(p++, 0xe320 | NM_HI1(kernel_entry));
stw_p(p++, NM_HI2(kernel_entry));
@@ -841,6 +843,9 @@ static void write_bootloader_nanomips(uint8_t *base,
uint64_t run_addr,
static void write_bootloader(uint8_t *base, uint64_t run_addr,
uint64_t kernel_entry)
{
+ const char pci_pins_cfg[PCI_NUM_PINS] = {
+ 10, 10, 11, 11 /* PIIX IRQRC[A:D] */
+ };
uint32_t *p;
/* Small bootloader */
@@ -915,6 +920,20 @@ static void write_bootloader(uint8_t *base, uint64_t
run_addr,
#undef cpu_to_gt32
+ /*
+ * The PIIX ISA bridge is on PCI bus 0 dev 10 func 0.
+ * Load the PIIX IRQC[A:D] routing config address, then
+ * write routing configuration to the config data register.
+ */
+ bl_gen_write_u32(&p, /* GT_PCI0_CFGADDR */
+ cpu_mips_phys_to_kseg1(NULL, 0x1be00000 + 0xcf8),
+ tswap32((1 << 31) /* ConfigEn */
+ | PCI_BUILD_BDF(0, PIIX4_PCI_DEVFN) << 8
+ | PIIX_PIRQCA));
+ bl_gen_write_u32(&p, /* GT_PCI0_CFGDATA */
+ cpu_mips_phys_to_kseg1(NULL, 0x1be00000 + 0xcfc),
+ tswap32(ldl_be_p(pci_pins_cfg)));
+
bl_gen_jump_kernel(&p,
true, ENVP_VADDR - 64,
/*
--
2.39.0
- [PATCH v4 00/30] This series consolidates the implementations of the PIIX3 and PIIX4 south, Bernhard Beschow, 2022/12/21
- [PATCH v4 01/30] hw/mips/malta: Introduce PIIX4_PCI_DEVFN definition, Bernhard Beschow, 2022/12/21
- [PATCH v4 02/30] hw/mips/malta: Set PIIX4 IRQ routes in embedded bootloader,
Bernhard Beschow <=
- [PATCH v4 06/30] hw/i386/pc_piix: Associate pci_map_irq_fn as soon as PCI bus is created, Bernhard Beschow, 2022/12/21
- [PATCH v4 05/30] hw/usb/hcd-uhci: Introduce TYPE_ defines for device models, Bernhard Beschow, 2022/12/21
- [PATCH v4 10/30] hw/isa/piix3: Create USB controller in host device, Bernhard Beschow, 2022/12/21
- [PATCH v4 03/30] hw/isa/piix4: Correct IRQRC[A:D] reset values, Bernhard Beschow, 2022/12/21
- [PATCH v4 09/30] hw/i386/pc: No need for rtc_state to be an out-parameter, Bernhard Beschow, 2022/12/21
- [PATCH v4 19/30] hw/isa/piix3: Drop the "3" from PIIX base class, Bernhard Beschow, 2022/12/21
- [PATCH v4 12/30] hw/core: Introduce proxy-pic, Bernhard Beschow, 2022/12/21
- [PATCH v4 15/30] hw/isa/piix3: Wire up ACPI interrupt internally, Bernhard Beschow, 2022/12/21
- [PATCH v4 11/30] hw/isa/piix3: Create power management controller in host device, Bernhard Beschow, 2022/12/21
- [PATCH v4 21/30] hw/isa/piix4: Remove unused inbound ISA interrupt lines, Bernhard Beschow, 2022/12/21