[Qemu-commits] [qemu/qemu] 5c78d6: hw/ds1338: Fix conversion between 12 hours and 24 ...

[GitHub]

  Branch: refs/heads/master
  Home:   https://github.com/qemu/qemu
  Commit: 5c78d6a84b504e831adc8f1917cde0c79061dff0
      
https://github.com/qemu/qemu/commit/5c78d6a84b504e831adc8f1917cde0c79061dff0
  Author: Antoine Mathys <address@hidden>
  Date:   2013-02-28 (Thu, 28 Feb 2013)

  Changed paths:
    M hw/ds1338.c

  Log Message:
  -----------
  hw/ds1338: Fix conversion between 12 hours and 24 hours modes.

The proper mapping between 24 hours and 12 hours modes is:
0       12 AM
1-11    1-11 AM
12      12 PM
13-23   1-11 PM
Fix code accordingly.

Signed-off-by: Antoine Mathys <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 6e392787c85809671033ec419d8e8ecf684d55da
      
https://github.com/qemu/qemu/commit/6e392787c85809671033ec419d8e8ecf684d55da
  Author: Peter Maydell <address@hidden>
  Date:   2013-02-28 (Thu, 28 Feb 2013)

  Changed paths:
    M hw/pflash_cfi01.c

  Log Message:
  -----------
  hw/pflash_cfi01: Make read after byte-write or erase return status

The Intel flash command set requires that a read operation after
doing a 'single byte write' command returns the status register;
add this case to pflash_read() so we return the correct information.
Similarly, the case for the 0x28 flavour of block erase was missing.

Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Peter Crosthwaite <address@hidden>
Tested-by: Peter Crosthwaite <address@hidden>
Message-id: address@hidden


  Commit: 1be97bf22447088adebf23b1ca508d4bb00f853c
      
https://github.com/qemu/qemu/commit/1be97bf22447088adebf23b1ca508d4bb00f853c
  Author: Peter Maydell <address@hidden>
  Date:   2013-02-28 (Thu, 28 Feb 2013)

  Changed paths:
    M hw/pflash_cfi01.c

  Log Message:
  -----------
  hw/pflash_cfi01: Treat read in unknown command state as read

The code for handling the default "unknown command state" case in
pflash_read in pflash_cfi01.c comments "reset state & treat it as
a read". However the code doesn't actually do this. Moving the
default case to the top of the switch so it can fall through into
the read case brings this file into line with pflash_cfi02 and
makes the code behave as the comments suggest.

The pflash_cfi01 code has always had this bug -- it was presumably
introduced when the original author copied the cfi02 code and
rearranged the order of the switch statement without noticing
that the default case relied on the fall-through.

Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Peter Crosthwaite <address@hidden>
Tested-by: Peter Crosthwaite <address@hidden>
Message-id: address@hidden


  Commit: c6205ddf6cff202ac0ce6621987cd3de8b57adee
      
https://github.com/qemu/qemu/commit/c6205ddf6cff202ac0ce6621987cd3de8b57adee
  Author: Peter Crosthwaite <address@hidden>
  Date:   2013-02-28 (Thu, 28 Feb 2013)

  Changed paths:
    M hw/arm_mptimer.c

  Log Message:
  -----------
  arm: mptimer: CamelCased type names

Trivial find replace on type names "timerblock" and "arm_mptimer_state" to
conform with QEMU coding style.

Signed-off-by: Peter Crosthwaite <address@hidden>
Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 845769fc6319d308a39a78734c6dc03fa93ff2c5
      
https://github.com/qemu/qemu/commit/845769fc6319d308a39a78734c6dc03fa93ff2c5
  Author: Peter Crosthwaite <address@hidden>
  Date:   2013-02-28 (Thu, 28 Feb 2013)

  Changed paths:
    M hw/a9mpcore.c
    M hw/arm11mpcore.c

  Log Message:
  -----------
  arm: arm11mpcore, a9mpcore: CamelCased type names

To conform with QEMU coding style.

Signed-off-by: Peter Crosthwaite <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>


  Commit: cde4577f11cd557cfd48d752b7a0929d19eac9e9
      
https://github.com/qemu/qemu/commit/cde4577f11cd557cfd48d752b7a0929d19eac9e9
  Author: Peter Crosthwaite <address@hidden>
  Date:   2013-02-28 (Thu, 28 Feb 2013)

  Changed paths:
    M hw/a9mpcore.c
    M hw/arm11mpcore.c
    M hw/arm_mptimer.c

  Log Message:
  -----------
  arm: mptimer: Remove WDT distinction

In QEMU emulation, there is no functional difference between the ARM mpcore
private timers and watchdogs. Removed all the distinction between the two from
arm_mptimer.c and converted it to be just the mptimer. a9mpcore and arm11mpcore
just instantiate the same mptimer object twice to get both timer and WDT.

If in the future we want to make the WDT functionally different then we can use
either QOM hierarchy to derive WDT from from mptimer, or we can add a property
"is-wdt" or some such.

Signed-off-by: Peter Crosthwaite <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 9595978292e9a5b5f0ec77a9f6a0e724c10bf3b4
      
https://github.com/qemu/qemu/commit/9595978292e9a5b5f0ec77a9f6a0e724c10bf3b4
  Author: Peter Crosthwaite <address@hidden>
  Date:   2013-02-28 (Thu, 28 Feb 2013)

  Changed paths:
    M hw/a9mpcore.c

  Log Message:
  -----------
  arm: a9mpcore: remove old_timer_status field

This field was write only and thus unused. Removed.

Signed-off-by: Peter Crosthwaite <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 353575f0959234e1680622f747e20308c94505b7
      
https://github.com/qemu/qemu/commit/353575f0959234e1680622f747e20308c94505b7
  Author: Peter Crosthwaite <address@hidden>
  Date:   2013-02-28 (Thu, 28 Feb 2013)

  Changed paths:
    M hw/a9mpcore.c
    A hw/a9scu.c
    M hw/arm/Makefile.objs

  Log Message:
  -----------
  arm: a9mpcore: Coreify the SCU

Split the SCU in a9mpcore out into its own object definition. mpcore is now
just a container for the mpcore components.

Signed-off-by: Peter Crosthwaite <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>


  Commit: d7dfca0807a0f579d3ec985bf1220519420c4dfe
      
https://github.com/qemu/qemu/commit/d7dfca0807a0f579d3ec985bf1220519420c4dfe
  Author: Igor Mitsyanko <address@hidden>
  Date:   2013-02-28 (Thu, 28 Feb 2013)

  Changed paths:
    M default-configs/arm-softmmu.mak
    M hw/Makefile.objs
    A hw/sdhci.c
    A hw/sdhci.h

  Log Message:
  -----------
  hw/sdhci: introduce standard SD host controller

Device model for standard SD Host Controller Interface (SDHCI) compliant with
version 2.00 of SD association specification.

Signed-off-by: Peter Crosthwaite <address@hidden>
Signed-off-by: Igor Mitsyanko <address@hidden>
Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 80f4d9fcea86aeb3071750c199416cab9abd5c28
      
https://github.com/qemu/qemu/commit/80f4d9fcea86aeb3071750c199416cab9abd5c28
  Author: Peter Crosthwaite <address@hidden>
  Date:   2013-02-28 (Thu, 28 Feb 2013)

  Changed paths:
    M vl.c

  Log Message:
  -----------
  vl.c: allow for repeated -sd arguments

Allows for repeating of -sd arguments in the same way as -pflash and -mtdblock.

Acked-by: Igor Mitsyanko <address@hidden>
Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Peter Crosthwaite <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>


  Commit: b972b4e25340abdd23238bc8f3bdacbef533bd5a
      
https://github.com/qemu/qemu/commit/b972b4e25340abdd23238bc8f3bdacbef533bd5a
  Author: Peter Crosthwaite <address@hidden>
  Date:   2013-02-28 (Thu, 28 Feb 2013)

  Changed paths:
    M hw/xilinx_zynq.c

  Log Message:
  -----------
  xilinx_zynq: Added SD controllers

The Xilinx Zynq device has two SDHCI controllers. Added to the machine model.

Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Peter Crosthwaite <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>


  Commit: a7fd6915d84b20d5ff9ae287ddfabb9b222e7067
      
https://github.com/qemu/qemu/commit/a7fd6915d84b20d5ff9ae287ddfabb9b222e7067
  Author: Peter Crosthwaite <address@hidden>
  Date:   2013-02-28 (Thu, 28 Feb 2013)

  Changed paths:
    M hw/m25p80.c
    M hw/petalogix_ml605_mmu.c
    M hw/xilinx_zynq.c

  Log Message:
  -----------
  m25p80.c: Use QOM classes for part differentiation

Currently, M25P80 uses an object property to differentiate between flash parts.
Changed this over to use QOM sub-classes - the actual names of the different 
parts
are used to create a set of dynamic classes which passes the part info as class
data. The object no longer needs to search the known_devices table for itself,
instead it just gets its info from its own class.

Kept the intermediate class definition private to m25p80.c for the moment, as
the expectation is parts will only be added as new entries in the table. We can
factor out the TYPE_M25P80 abstraction into a header on a demand basis.

Signed-off-by: Peter Crosthwaite <address@hidden>
Message-id: address@hidden
Reviewed-by: Andreas Färber <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>


  Commit: e3f9d31c9899cc94e124b042d7d5353dbfd812ca
      
https://github.com/qemu/qemu/commit/e3f9d31c9899cc94e124b042d7d5353dbfd812ca
  Author: Peter Crosthwaite <address@hidden>
  Date:   2013-02-28 (Thu, 28 Feb 2013)

  Changed paths:
    M hw/cadence_gem.c

  Log Message:
  -----------
  cadence_gem: Flush queued packets

The device needs to check for queued RX packets when the RX path is re-enabled.

Signed-off-by: Peter Crosthwaite <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 1c5d07909aea7657c7c6b24223460150526369ba
      
https://github.com/qemu/qemu/commit/1c5d07909aea7657c7c6b24223460150526369ba
  Author: Peter Crosthwaite <address@hidden>
  Date:   2013-02-28 (Thu, 28 Feb 2013)

  Changed paths:
    M hw/cadence_gem.c

  Log Message:
  -----------
  cadence_gem: factor out can_rx() logic replication

The gem_receive() function replicates the logic for whether or not the device
can rx. Just call the actual gem_can_receive() function in place.

Signed-off-by: Peter Crosthwaite <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>


  Commit: ae80a3546f412c407199b9b7ebd52ac604361e10
      
https://github.com/qemu/qemu/commit/ae80a3546f412c407199b9b7ebd52ac604361e10
  Author: Peter Crosthwaite <address@hidden>
  Date:   2013-02-28 (Thu, 28 Feb 2013)

  Changed paths:
    M hw/cadence_gem.c

  Log Message:
  -----------
  cadence_gem: fix interrupt events

Bits in the ISR were continually mirroring their corresponding TX/RX SR bits.
This is incorrect. The ISR bits are only ever set at the time their
corresponding event occurs.

Signed-off-by: Peter Crosthwaite <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 5025388b5083f199b05cc252c2b031d9fc230391
      
https://github.com/qemu/qemu/commit/5025388b5083f199b05cc252c2b031d9fc230391
  Author: Peter Crosthwaite <address@hidden>
  Date:   2013-02-28 (Thu, 28 Feb 2013)

  Changed paths:
    M hw/cadence_gem.c

  Log Message:
  -----------
  cadence_gem: Don't reset rx desc pointer on rx_en

This doesn't happen in the real hardware. The Zynq TRM explicitly states that
this bit has no effect on the rx descriptor pointer ("The receive queue
pointer register is unaffected").

Signed-off-by: Peter Crosthwaite <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 288f1e3f87ec24abeac38399f175fe74243f7bc5
      
https://github.com/qemu/qemu/commit/288f1e3f87ec24abeac38399f175fe74243f7bc5
  Author: Peter Crosthwaite <address@hidden>
  Date:   2013-02-28 (Thu, 28 Feb 2013)

  Changed paths:
    M hw/cadence_gem.c

  Log Message:
  -----------
  cadence_gem: Add debug msgs for rx desc movement

Add some helpful messages that show the rx descriptor pointer moving as packets
are rxed.

Signed-off-by: Peter Crosthwaite <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>


Compare: https://github.com/qemu/qemu/compare/a4bcea3d6794...288f1e3f87ec