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[Qemu-commits] [qemu/qemu] 34c6ad: target-i386: SSE4.1: fix pinsrb instr
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GitHub |
Subject: |
[Qemu-commits] [qemu/qemu] 34c6ad: target-i386: SSE4.1: fix pinsrb instruction |
Date: |
Mon, 01 Apr 2013 10:30:17 -0700 |
Branch: refs/heads/master
Home: https://github.com/qemu/qemu
Commit: 34c6addd4b22583e7b408c0d1452eab753cbfb62
https://github.com/qemu/qemu/commit/34c6addd4b22583e7b408c0d1452eab753cbfb62
Author: Aurelien Jarno <address@hidden>
Date: 2013-04-01 (Mon, 01 Apr 2013)
Changed paths:
M target-i386/translate.c
Log Message:
-----------
target-i386: SSE4.1: fix pinsrb instruction
gen_op_mov_TN_reg() loads the value in cpu_T[0], so this temporary should
be used instead of cpu_tmp0.
Reviewed-by: Richard Henderson <address@hidden>
Signed-off-by: Aurelien Jarno <address@hidden>
Commit: da5156cd9a62274839d6fa685cc52614886cc722
https://github.com/qemu/qemu/commit/da5156cd9a62274839d6fa685cc52614886cc722
Author: Aurelien Jarno <address@hidden>
Date: 2013-04-01 (Mon, 01 Apr 2013)
Changed paths:
M target-i386/ops_sse.h
Log Message:
-----------
target-i386: SSE4.2: fix pcmpgtq instruction
The "Intel 64 and IA-32 Architectures Software Developer's Manual" (at
least recent versions) clearly says that the comparison is signed.
Reviewed-by: Richard Henderson <address@hidden>
Signed-off-by: Aurelien Jarno <address@hidden>
Commit: 93e3c0ae69ae73d7f04ac378c5df6e98c7faa6dd
https://github.com/qemu/qemu/commit/93e3c0ae69ae73d7f04ac378c5df6e98c7faa6dd
Author: Aurelien Jarno <address@hidden>
Date: 2013-04-01 (Mon, 01 Apr 2013)
Changed paths:
M target-i386/ops_sse.h
Log Message:
-----------
target-i386: SSE4.2: fix pcmpXstri instructions
ffs1 returns the first bit set to one starting counting from the most
significant bit.
pcmpXstri returns the most significant bit set to one, starting counting
from the least significant bit.
Reviewed-by: Richard Henderson <address@hidden>
Signed-off-by: Aurelien Jarno <address@hidden>
Commit: 2b8d7e9d728fe2b7c8ffb9859368fb2b5c0bf833
https://github.com/qemu/qemu/commit/2b8d7e9d728fe2b7c8ffb9859368fb2b5c0bf833
Author: Aurelien Jarno <address@hidden>
Date: 2013-04-01 (Mon, 01 Apr 2013)
Changed paths:
M target-i386/ops_sse.h
Log Message:
-----------
target-i386: SSE4.2: fix pcmpXstrm instructions
pcmpXstrm instructions returns their result in the XMM0 register and
not in the first operand.
Reviewed-by: Richard Henderson <address@hidden>
Signed-off-by: Aurelien Jarno <address@hidden>
Commit: 649ad05ed4133d3a48d43881aa9351c024d9cdc1
https://github.com/qemu/qemu/commit/649ad05ed4133d3a48d43881aa9351c024d9cdc1
Author: Aurelien Jarno <address@hidden>
Date: 2013-04-01 (Mon, 01 Apr 2013)
Changed paths:
M target-i386/ops_sse.h
Log Message:
-----------
target-i386: SSE4.2: fix pcmpXstrX instructions in "Ranges" mode
Fix the order of the of the comparisons to match the "Intel 64 and
IA-32 Architectures Software Developer's Manual".
Reviewed-by: Richard Henderson <address@hidden>
Signed-off-by: Aurelien Jarno <address@hidden>
Commit: b27a6cacb73ca006c6995ca5c3db7347333ba7f4
https://github.com/qemu/qemu/commit/b27a6cacb73ca006c6995ca5c3db7347333ba7f4
Author: Aurelien Jarno <address@hidden>
Date: 2013-04-01 (Mon, 01 Apr 2013)
Changed paths:
M target-i386/ops_sse.h
Log Message:
-----------
target-i386: SSE4.2: fix pcmpXstrX instructions in "Equal each" mode
pcmpXstrX instructions in "Equal each" mode force both invalid element
pair to true. It means (upper - MAX(valids, validd)) bits should be set
to 1, not (upper - MAX(valids, validd) + 1).
Reviewed-by: Richard Henderson <address@hidden>
Signed-off-by: Aurelien Jarno <address@hidden>
Commit: 75c9527e190231fbc2fd8470e132f360e70206be
https://github.com/qemu/qemu/commit/75c9527e190231fbc2fd8470e132f360e70206be
Author: Aurelien Jarno <address@hidden>
Date: 2013-04-01 (Mon, 01 Apr 2013)
Changed paths:
M target-i386/ops_sse.h
Log Message:
-----------
target-i386: SSE4.2: fix pcmpXstrX instructions in "Equal ordered" mode
The inner loop should only change the current bit of the result, instead
of the whole result.
Reviewed-by: Richard Henderson <address@hidden>
Signed-off-by: Aurelien Jarno <address@hidden>
Commit: e4eba27e29114842978234a44c92b2a945a6b46d
https://github.com/qemu/qemu/commit/e4eba27e29114842978234a44c92b2a945a6b46d
Author: Aurelien Jarno <address@hidden>
Date: 2013-04-01 (Mon, 01 Apr 2013)
Changed paths:
M target-i386/ops_sse.h
Log Message:
-----------
target-i386: SSE4.2: fix pcmpXstrX instructions with "Masked(-)" polarity
valids can equals to -1 if the reg/mem string is empty. Change the
expression to have an empty xor mask in that case.
Reviewed-by: Richard Henderson <address@hidden>
Signed-off-by: Aurelien Jarno <address@hidden>
Commit: 83f7dc28ca7cb422f88caf3923bf078abb4e4dea
https://github.com/qemu/qemu/commit/83f7dc28ca7cb422f88caf3923bf078abb4e4dea
Author: Aurelien Jarno <address@hidden>
Date: 2013-04-01 (Mon, 01 Apr 2013)
Changed paths:
M target-i386/cpu.c
Log Message:
-----------
target-i386: enable SSE4.1 and SSE4.2 in TCG mode
Reviewed-by: Richard Henderson <address@hidden>
Signed-off-by: Aurelien Jarno <address@hidden>
Commit: c334a3880c02d1d8299ed54057e3fffd99ad2048
https://github.com/qemu/qemu/commit/c334a3880c02d1d8299ed54057e3fffd99ad2048
Author: Aurelien Jarno <address@hidden>
Date: 2013-04-01 (Mon, 01 Apr 2013)
Changed paths:
M target-i386/fpu_helper.c
M target-i386/ops_sse.h
Log Message:
-----------
target-i386: SSE4.2: use clz32/ctz32 instead of reinventing the wheel
Reviewed-by: Richard Henderson <address@hidden>
Signed-off-by: Aurelien Jarno <address@hidden>
Commit: 174d4d215fb49b4d43196e62f22c2533431b260e
https://github.com/qemu/qemu/commit/174d4d215fb49b4d43196e62f22c2533431b260e
Author: Aurelien Jarno <address@hidden>
Date: 2013-04-01 (Mon, 01 Apr 2013)
Changed paths:
M tcg/mips/tcg-target.c
M tcg/mips/tcg-target.h
Log Message:
-----------
tcg/mips: Implement muls2_i32
Reviewed-by: Richard Henderson <address@hidden>
Signed-off-by: Aurelien Jarno <address@hidden>
Compare: https://github.com/qemu/qemu/compare/c7b4c36714a4...174d4d215fb4
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